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Commit 5b02a99e authored by Kevin Bracey's avatar Kevin Bracey
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RISC OS 3.71 version taken

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TestSrc/Begin
View file @ 5b02a99e
......@@ -284,6 +284,20 @@ ts_ROM_bvectors
SetMode SVC32_mode,$tmp
MEND
[ StrongARM_POST
; ensure 26-bit mode for StrongARM or ARM 8 (since there is no 26 bit configuration)
MACRO
Ensure26bit_ARM8A $tmp
ARM_read_ID $tmp
AND $tmp, $tmp, #&F000
CMP $tmp, #&A000
CMPNE $tmp, #&8000
mrs EQ, $tmp, CPSR_all
BICEQ $tmp, $tmp, #&10
msr EQ, CPSR_all, $tmp
MEND
]
;
; Define an area of storage with the required set of data bus patterns
; These are used both for testing the complete width of the data bus
......@@ -481,8 +495,13 @@ ts_User_startup ROUT
ADDS r1,r1,r1 ; then shift it into carry
BCC ts_Self_test_end ; POR bit clear - do soft reset.
; it's a power-on reset, so assume we can't be in 32-bit mode
; it's a power-on reset, so assume we can't be in 32-bit mode for ARM 6/7
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r0
]
MOV_fiq r12_fiq, #R_HARD
B ts_Self_test_startup
|
......@@ -501,6 +520,11 @@ ts_User_startup ROUT
ts_Forced_startup ROUT
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r0
]
MOV_fiq r12_fiq, #R_TESTED
B ts_Self_test_startup
......@@ -508,6 +532,11 @@ ts_Forced_startup ROUT
ts_Dealer_startup ROUT
[ StrongARM_POST
; make sure we are in 26-bit mode (ARM 6/7 reset in 26-bit config)
; note that MOV_fiq macro assumes 26-bit, so must sort this now
Ensure26bit_ARM8A r4
]
MOV_fiq r12_fiq, #R_EXTERN
LDR r4,%FT02 ; make a pointer to signon string
......@@ -538,10 +567,17 @@ ts_Self_test_startup ROUT
MOV r2, #IOMD_Base
LDRB r0, [r2, #IOMD_ID0]
CMP r0, #&98
CMP r0, #&E7
LDRB r0, [r2, #IOMD_ID1]
CMPEQ r0, #&5B
BNE %FT10
CMPEQ r0, #&D4
BEQ %FT10
[ RO371Timings
MOV r0, #0 ;Calling from POST
BL TimeCPU ;just sets things according to assumed bus speeds for each IOMD id, in this case
| ; else if not RO371Timings
;
; PSwindell wants all prescalers set to divide by 1
......@@ -557,6 +593,7 @@ ts_Self_test_startup ROUT
;
LDRB r1, [r2, #IOMD_ROMCR0]
AND r1, r1, #&40 ; clear all but 16-bit mode bit
[ :LNOT: AutoSpeedROMS
[ NormalSpeedROMS
;Normal code
......@@ -570,12 +607,16 @@ ts_Self_test_startup ROUT
! 0, "*** WARNING *** Slow ROM version ment for PSwindell"
]
STRB r1, [r2, #IOMD_ROMCR0]
STRB r1, [r2, #IOMD_ROMCR1] ; and do the same for extension ROMs (just in case)
|
MOV r0, #0 ;Don't muck with the CPU coprocessor regs
BL TimeCPU ;This times the memory bus & sets the ROM speed accordingly
]
] ;RO371Timings conditional
;
10
]
......@@ -609,15 +650,27 @@ ts_InitVIDC
STRNE r0, [r1]
BNE %BT10
[ StrongARM
;just too horrible to fix POST for StrongARM (Architecture 4) at the moment
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&A000 ;if we are a StrongARM...
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
[ :LNOT: StrongARM_POST
;skip POST for StrongARM or ARM8
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&A000 ;if we are a StrongARM...
CMPNE r0,#&8000 ;or an ARM8...
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
]
[ ARM810support :LAND: (:LNOT: ARM810_POST)
;just too horrible to fix POST for ARM 8 at the moment
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&8000 ;if we are an ARM 8
LDREQ r0,=C_WARMSTART ;the colour that indicates no POST performed
STREQ r0,[r1]
BEQ ts_Hardstart ;RISC OS - right now!
]
LDR r0,=C_ARMOK ; set initial screen colour
STR r0, [r1]
......@@ -1162,6 +1215,27 @@ ts_CAMtest
;
ts_restore_physical
[ StrongARM_POST
;make sure ARM810 cache or StrongARM data cache is cleaned/flushed, because we are going to remap
ARM_read_ID r5
AND r5,r5,#&F000
CMP r5,#&8000
BNE %FT22
;ARM810
;;; ARM8_cleanflush_IDC r5 ;not implemented yet
B %FT24
22
CMP r5,#&A000
BNE %FT24
;StrongARM
;tricky...we'll read 16k of data in current ROM space, to act as clean and flush of current data
MOV r3,pc
BIC r3,r3,#31 ;32 byte aligned
ARMA_clean_DC r3,r5,r7
24
] ;StrongARM_POST
MOV r5, pc ; obtain current address
SUB r5, r5,#PhysSpace ; adjust to point to unmapped version
MOV r5, r5, LSR #20 ; divide by 1MB
......@@ -1174,8 +1248,20 @@ ts_restore_physical
ADD r3, r3, #DRAMOffset_L1PT
STR r7, [r3, r5, LSL #2] ; store replacement entry in L1 (not U,C or B)
[ StrongARM_POST
;flush cache if ARM 6/7 (ARM 8,StrongARM already sorted, above)
;flush TLB(s)
ARM_read_ID r4
AND r4,r4,#&F000
CMP r4,#&8000 ;ARM 8?
CMPNE r4,#&A000 ;or StrongARM?
MCRNE ARM_config_cp,0,R0,ARM67_cacheflush_reg,C0,0 ;flush 6/7 cache
MCRNE ARM_config_cp,0,R0,ARM67_TLBflush_reg,C0,0 ;flush 6/7 TLB
MCREQ ARM_config_cp,0,R0,ARM8A_TLB_reg,C7,0 ;flush 8/StrongARM TLB(s)
|
SetCop r7, CR_IDCFlush ; flush cache + TLB just in case
SetCop r7, CR_TLBFlush ; (data written is irrelevant)
]
; The ROM should now be mapped at the present address less PhysSpace, which is where it
; would be if the MMU were turned off.
......@@ -1184,9 +1270,15 @@ ts_restore_physical
SUB pc,pc,r4
NOP ; this instruction is skipped
MOV r7, #MMUC_D ; Now turn the MMU off
; now turn the MMU off, also ensures 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r7, #MMUC_D
SetCop r7, CR_Control
[ StrongARM_POST
Ensure26bit_ARM8A r7
MOV r7, #MMUC_D ;avoid corrupting r7, just in case
]
B ts_VIDCtest
;
......@@ -1223,10 +1315,10 @@ ts_VIDCtest
MOV r3, #IOMD_Base
LDRB r0, [r3, #IOMD_ID0]
CMP r0, #&98
CMP r0, #&E7
LDRB r0, [r3, #IOMD_ID1]
CMPEQ r0, #&5B ; skip Virq test on Morris
BEQ %FT10
CMPEQ r0, #&D4 ; skip Virq test on Morris
BNE %FT10
]
BL ts_VIDC_period
......
TestSrc/Ioc
View file @ 5b02a99e
......@@ -3,7 +3,7 @@
TTL RISC OS 2+ POST IO controller
;
; This initial IOC test simply reports the content of the IRQ and FIRQ
; registers, to show any unexpected pending IRQs.
; registers, to show any unexpected pending IRQs.
; Certain of these should really be cleared, and the effect of an
; interrupt tested.
;
......@@ -77,8 +77,9 @@ ts_IOCstat
LDR r1,=ts_IOMD_ID
CMPS r0,r1 ; check IOMD identity
[ MorrisSupport
LDRNE r1,=ts_IOMD_IDmorris ; allow for Morris variant
CMPNES r0,r1
;; LDRNE r1,=ts_IOMD_IDmorris ; allow for Morris variant
;; CMPNES r0,r1
CMPNE r0,r0 ;insist on not failing (allow 7500,7500FE...)
]
MOV r0,r0,LSL #16
LDRB r1,[r3,#IOMD_VERSION]
......@@ -98,5 +99,5 @@ ts_IOCstat
MOV pc,r14
]
END
END
TestSrc/Mem1IOMD
View file @ 5b02a99e
......@@ -42,10 +42,10 @@ ts_LineTest
MOV r12, #IOMD_Base
LDRB r0, [r12, #IOMD_ID0]
CMP r0, #&98
CMP r0, #&E7
LDRB r0, [r12, #IOMD_ID1]
CMPEQ r0, #&5B
BNE ts_LineTestIOMD ; NOT MORRIS assume Medusa hardware
CMPEQ r0, #&D4
BEQ ts_LineTestIOMD ; Medusa hardware, else assume Morris
;
; ts_LineTest for Morris
......@@ -54,9 +54,14 @@ ts_LineTest
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMWID]
MOV r0,#MMUC_D ; enable 32-bit addressing of data
; enable 32-bit addressing of data, also forces 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r0,#MMUC_D
SetCop r0,CR_Control
[ StrongARM_POST
Ensure26bit_ARM8A r0
]
MOV r0,#0
MOV_fiq r9,r0 ; r9-fiq records low DRAM address for use elsewhere
......@@ -344,9 +349,14 @@ ts_LineTestIOMD
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMCR]
MOV r0,#MMUC_D ; enable 32-bit addressing of data
; enable 32-bit addressing of data, also forces 26 bit mode, if ARM 6/7 (since P bit zero)
MOV r0,#MMUC_D
SetCop r0,CR_Control
[ StrongARM_POST
Ensure26bit_ARM8A r10
]
MOV r10, #0 ; indicate no RAM found yet
MOV r9, #IOMD_DRAMCR_DRAM_Small ; bit to OR into DRAMCR
MOV r12, #DRAM0PhysRam
......
TestSrc/Mem2
View file @ 5b02a99e
;> MEM2C
;
;
; RISC OS 2+ BOOT TEST SOFTWARE
; MEMORY TEST 2 VERSION A.
; BRIAN RICE 30-10-89
; 06-Apr-90 ArtG 0.1 Test variable memory size
;
; This file will perform a simple test on all DRAM.
; The test code for this test was taken from thhe A680 Quick memory
; test software. The software was copied straight but the number of times
; The test code for this test was taken from thhe A680 Quick memory
; test software. The software was copied straight but the number of times
; the test looped arround was cut down to two loops, because of time
; constraints when testing the memory.
......@@ -50,8 +50,8 @@ test_mem_quit
ANDS r2,r2,#1 ; calculate expected data
ADREQ r12,%20 ; and load suitable message
ADRNE r12,%21
MOVS r0,r0 ; with zero flag set for PASS.
10
MOVS r0,r0 ; with zero flag set for PASS.
10
LDR pc,[r13,#Test_wks_return1]
; Fail messages indicate incorrect data read after WRote 0 or Wrote 1
......@@ -84,7 +84,7 @@ test_mem_code
STR r14, [r13, #Test_wks_return2]
;
; Copy the ram test code into low ram, modifying MOV instructions
; to MVN in accordance with the test pattern.
; to MVN in accordance with the test pattern.
;
ADR r1, test_mem_template
ADD r2, r13, #Test_code_off
......@@ -149,7 +149,7 @@ test_mem_code
; The following code is copied (and modified) into RAM for execution
;
test_mem_template
test_mem_template
ROUT
STR r0, test_mem_stadd ; save initial RAM address
STR r13, test_mem_base ; save test area base address
......@@ -188,7 +188,7 @@ test_mem_template
CMPEQ r11, #0 ; Converted to cmneq if bit = 1
CMPEQ r12, #0 ; Converted to cmneq if bit = 1
CMPEQ r13, #0 ; Converted to cmneq if bit = 1
test_mem_chk
test_mem_chk
BNE %F5 ; go report fault data
CMP r0, r14
BLO %B1 ; else loop for next batch
......@@ -201,7 +201,7 @@ test_mem_chk
; the first failing address and data.
; Note that the test instructions are copied to %8 to permit individual
; execution, and %7 is overwritten with an instruction used to copy
; the failing data into r1. Change this code very carefully !
; the failing data into r1. Change this code very carefully !
5
LDR r14,%2 ; Obtain first test in the set
......@@ -218,8 +218,8 @@ test_mem_chk
; r14 => failing instruction
LDR r1,[r14,#4]! ;fetch next instruction
AND r1,r1,#&f0000 ;make an instruction
MOV r1,r1,LSR #16 ;to copy the next register
AND r1,r1,#&f0000 ;make an instruction
MOV r1,r1,LSR #16 ;to copy the next register
ORR r1,r1,#&E1000000 ;down to r1
ORR r1,r1,#&00A00000 ;e.g. CMPEQ r10,#0
ORR r1,r1,#&00001000
......@@ -243,6 +243,27 @@ test_mem_template_end
ROUT
ts_remap_ttab
[ StrongARM_POST
;make sure ARM810 cache or StrongARM data cache is cleaned/flushed, because we are going to remap
ARM_read_ID r3
AND r3,r3,#&F000
CMP r3,#&8000
BNE %FT22
;ARM810
;;; ARM8_cleanflush_IDC r3 ;not implemented yet
B %FT24
22
CMP r3,#&A000
BNE %FT24
;StrongARM
;tricky...we'll read 16k of data in current ROM space, to act as clean and flush of current data
MOV r3,pc
BIC r3,r3,#31 ;32 byte aligned
ARMA_clean_DC r3,r4,r5
24
] ;StrongARM_POST
MOV r2,#FixedAreasL2Size
ADD r0,r0,r2 ; point to locations in PhysSpace
ADD r0,r0,#PhysSpace
......@@ -255,7 +276,7 @@ ts_remap_ttab
SUBS r2,r2,#(8*4)
BNE %BT10
SUB r9,r1,r0 ; r9 = offset from original to copy
SUB r9,r1,r0 ; r9 = offset from original to copy
ADD r0, r0, #DRAMOffset_L1PT-DRAMOffset_L2PT ; r0 -> copy of L1Phys
SUB r10, r0, #PhysSpace ; keep real address of L1PT for MMU
ADD r2,r0,#((1 :SHL: (32-20))*4) ; size of L1PT - 1 word per meg of memory
......@@ -265,14 +286,27 @@ ts_remap_ttab
SUBEQ r3,r3,r9 ; adjust the page table base address
STREQ r3,[r0,#-4]
CMPS r0,r2 ; repeat for all the level 1 table
BNE %BT11
BNE %BT11
SetCop r10, CR_TTabBase ; set up MMU pointer to L1
[ StrongARM_POST
;flush cache if ARM 6/7 (ARM 8,StrongARM already sorted, above)
;flush TLB(s)
ARM_read_ID r4
AND r4,r4,#&F000
CMP r4,#&8000 ;ARM 8?
CMPNE r4,#&A000 ;or StrongARM?
MCRNE ARM_config_cp,0,R0,ARM67_cacheflush_reg,C0,0 ;flush 6/7 cache
MCRNE ARM_config_cp,0,R0,ARM67_TLBflush_reg,C0,0 ;flush 6/7 TLB
MCREQ ARM_config_cp,0,R0,ARM8A_TLB_reg,C7,0 ;flush 8/StrongARM TLB(s)
|
SetCop r0, CR_IDCFlush ; flush cache + TLB just in case
SetCop r0, CR_TLBFlush ; (data written is irrelevant)
]
MOV pc,r14
END
TestSrc/Mem3
View file @ 5b02a99e
......@@ -36,6 +36,10 @@ ts_CRCsize * (2 * 4)
ts_ROM_checksum
;StrongARM_POST issue:
;ARM810 - this will probably go bang! because ARM810 aborts if the processor
; vectors (00 - 1C) are read in 26-bit mode
MOV r1, #&00 ; initialise accumulator
LDR r0, =PhysROM ; initialise pointer
LDR r2, [r0, #ts_ROMSIZE] ; initialise endstop
......
Version
View file @ 5b02a99e
......@@ -4,8 +4,8 @@
GBLS VString
GBLS Date
Version SETA 370
VString SETS "3.70"
Date SETS "30 Jul 1996"
Version SETA 371
VString SETS "3.71"
Date SETS "19 Feb 1997"
END
s/AMBControl/memmap
View file @ 5b02a99e
......@@ -235,6 +235,33 @@ AMB_movepagesout_L2PT ROUT
ARMA_drain_WB EQ ;because L2PT area for AppSpace will be bufferable
Pull "r0-r8,pc"
[ ARM810support
;Previously supported ARMs all tolerate cache (clean and) flush _after_
;remapping - ARMs 6,7 because there is no clean, StrongARM because the cache
;writebacks use physical address.
;ARM810 does not support clean of writeback cache after remapping, since
;writebacks use virtual address. Rather than completely restructure code,
;this routine is called before remapping where necessary, and cleans/flushes
;if it finds we are running on ARM 810.
;
;corrupts r3
;
AMB_cachecleanflush_ifARM810
ARM_read_ID r3
AND r3,r3,#&F000
CMP r3,#&8000
MOVNE pc,lr ;not ARM8
[ ARM810cleanflushbroken
Push "lr"
ARM8_cleanflush_IDC r3,lr
Pull "pc"
|
ARM8_cleanflush_IDC r3
MOV pc,lr
]
] ;ARM810support
;**************************************************************************
; AMB_SetMemMapEntries:
;
......@@ -285,6 +312,9 @@ AMB_SetMemMapEntries ROUT
;could be an optimise here if source is FreePool and we know that FreePool
;has not been used - ie. no need to clean/flush cache(s) - not done yet (requires
;sorting of Wimp_ClaimFreeMemory)
[ ARM810support
BL AMB_cachecleanflush_ifARM810
]
MOV r3,r5
BL AMB_movepagesout_L2PT
BL AMB_movepagesin_L2PT
......@@ -293,6 +323,9 @@ AMB_SetMemMapEntries ROUT
;all pages sourced from same old logical page 'nowhere'
AMB_smme_mapin
[ ARM810support
BL AMB_cachecleanflush_ifARM810
]
MOV r3,r5
BL AMB_movepagesin_L2PT
BL AMB_movepagesin_CAM
......@@ -303,14 +336,22 @@ AMB_smme_mapin
;all pages destined for same new logical page 'nowhere'
AMB_smme_mapout
[ ARM810support
BL AMB_cachecleanflush_ifARM810
]
LDR r3,=DuffEntry
BL AMB_movepagesout_L2PT
BL AMB_movepagesout_CAM
;(clean and) flush cache(s) appropriately
;(clean and) flush cache(s) appropriately, then flush TLB(s)
AMB_smme_cachecleanflush
ARM_read_ID r0
AND r0,r0,#&F000
[ ARM810support
CMP r0,#&8000 ;cache clean/flush done before remapping if ARM810
ARM8_flush_TLB EQ
Pull "r0-r4,r7-r11, pc",EQ
]
CMP r0,#&A000
ARM67_flush_cache NE
ARM67_flush_TLB NE
......@@ -389,11 +430,16 @@ AMB_smme_StrongARM_flushrange
Pull "r0-r4,r7-r11, pc"
AMB_smme_TLBflush
[ ARM810support
;there is a general macro, should have used this before anyway
ARM_flush_TLB r0
|
ARM_read_ID r0
AND r0,r0,#&F000
CMP r0,#&A000
ARM67_flush_TLB NE
ARMA_flush_TLBs EQ
]
AMB_smme_exit
Pull "r0-r4,r7-r11, pc"
......
s/ARM600
View file @ 5b02a99e
This diff is collapsed.
s/ChangeDyn
View file @ 5b02a99e
......@@ -3283,6 +3283,15 @@ DoTheGrowPagesSpecified
BLEQ dtgps_SAcleanflush
]
[ ARM810support
;
; ARM810 has writeback cache too
;
ARM_number r0
CMP r0,#8
BLEQ dtgps_810cleanflush
]
; now move the pages
LDR r2, TotalAmount ; amount moving
......
s/Copro15ops
View file @ 5b02a99e
......@@ -18,7 +18,8 @@
;and cater for ARM 6,7,8,A (A=StrongARM).
;Routines detect which ARM directly by reading ARM ID register (avoids memory reads).
; Created by MJS, 24-01-96
; 24-01-96 MJS Created
; 07-10-96 MJS Updated for proper ARM 810 support (not needed for RO 3.70)
ARM_config_cp CP 15 ;coprocessor number for configuration control
......@@ -37,6 +38,8 @@ ARM8A_TLB_reg CN 8 ;TLB operations, ARMs 8 or StrongARM
ARM8_cacheLD_reg CN 9 ;cache lock-down, ARM 8
ARM8_TLBLD_reg CN 10 ;TLB lock-down, ARM 8
ARM8_CTC_reg CN 15 ;Clock and test configuration
ARMA_TCI_reg CN 15 ;Test,Clock and Idle control
;so that AASM will accept the general value for MCR CRm field
......@@ -165,9 +168,174 @@ C15 CN 15
MEND
;
; -------------- ARM 8 only ----------------------------------------------
; -------------- ARM 810 only ----------------------------------------------
;
[ ARM810support
;turn off branch prediction
; - the forced mispredicted branch ensures that the predictor is trapped in
; this code segment when turned off
; - corrupts $temp and status flags
;
MACRO
ARM8_branchpredict_off $temp
01
ARM_read_control $temp
BIC $temp,$temp,#&800 ;z bit (branch prediction)
ARM_write_control $temp
SEC ;set carry flag
BCC %BT01
MEND
;turn on branch prediction
MACRO
ARM8_branchpredict_on $temp
ARM_read_control $temp
ORR $temp,$temp,#&800 ;z bit (branch prediction)
ARM_write_control $temp
MEND
;flush branch prediction, which is sufficient for an IMB (instruction memory
;barrier) on ARM 810, BUT...
; - intended for in line use only, where efficiency matters, or SWI call is
; awkward
; - general code should use SWI OS_SynchroniseCodeAreas to implement
; an IMB (instruction memory barrier) in future proof, ARM independent way
; - kernel code may use this without regard to which ARM running - ie. assumed
; harmless on other ARMs
;
MACRO
ARM8_branchpredict_flush
SUB PC,PC,#4 ;flush, because PC is written by data op
MEND
;clean cache entry
; - segment,index spec in $reg
; - bits 4..6 = segment (0..7)
; - bits 26..31 = index (0..63)
; - all other bits zero
MACRO
ARM8_clean_IDCentry $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM8A_cache_reg,C11,1
MEND
;flush cache entry - segment,index spec in $reg, as for ARM8_clean_IDCentry
MACRO
ARM8_flush_IDCentry $reg,$cond
MCR$cond ARM_config_cp,0,$reg,ARM8A_cache_reg,C7,1
MEND
;clean and flush cache entry - segment,index spec in $reg, as for ARM8_clean_IDCentry
;
;if ARM810cleanflushbroken is TRUE, interrupts *must* be currently diabled (see below)
;
MACRO
ARM8_cleanflush_IDCentry $reg,$cond
[ ARM810cleanflushbroken
ARM8_clean_IDCentry $reg,$cond
ARM8_flush_IDCentry $reg,$cond
|
MCR$cond ARM_config_cp,0,$reg,ARM8A_cache_reg,C15,1
]
MEND
;fully clean and flush cache (assumes no locked-down entries to preserve)
;
;if ARM810cleanflushbroken is TRUE, then we have to make sure interrupts are disabled during