Commit 53aadeeb authored by Stewart Brodie's avatar Stewart Brodie
Browse files

Bug fixes only.

Detail:
  "Podule" number now displayed again in *ROMModule output - flag
     preservation issue caused it to disappear in 5.23.
  *Eval output no longer misses its trailing space, neither do "Podule" or
    "Extn ROM" in *ROMModules output.
  Heap manager now works again in non-SVC modes.
  Exception dump now contains faked up 26-bit PC+PSR lookalike.
Admin:
  Assembled.
parent b4016e9c
......@@ -205,7 +205,7 @@ SafeNaffExtension
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Here's the bit that gets returned to if the heap op was done in the
; background. Pick up the registers, look at the saved PC to see if error
; background. Pick up the registers, look at the saved PSR to see if error
; return or OK.
; This bit musn't be in range of the IRQ Heap Op checking!!!
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -255,7 +255,8 @@ heapopdoneinbackground ROUT
; Rest of universe ok
HeapEntry ROUT
Push lr ; lr is actually SPSR (sneaky)
Push lr
SavePSR lr ; hang on to interrupt state
; First check that we aren't in an interrupted Heap Op
WritePSRc SVC_mode+I_bit, R11
......@@ -297,13 +298,13 @@ inspect_IRQ_stack
; Could we poke these into the IRQ stack too...?
; would allow interruptible IRQ processes to do heap ops!!!
mrs ,lr, CPSR ; will be non-zero cause not in user mode
mrs ,lr, CPSR
STMIA R12, {R0-R3, R10, R11, lr}
Pull "R0-R3, lr"
iis_end ; store the registers in the info block
LDR R12, =HeapSavedReg_R0
STMIA R12, {R0-R4, stack} ;This is where the stacked PC (lr) points to (WT)
STMIA R12, {R0-R4, stack}
first_heap_address_to_trap ; because register saveblock now set.
LDR R12, [R12, #HeapReturnedReg_PSR-HeapSavedReg_R0]
......
......@@ -839,11 +839,19 @@ RESET1 ROUT
MOV R1, #0
LDR R1, [R1, #ExceptionDump]
STMIA R1, {R0-R14}
[ No26bitCode
MOV R0, #0
STR R0, [R1, #15*4]
[ No26bitCode
mrs ,R0, CPSR
STR R0, [R1, #16*4]
|
mrs ,R0, CPSR ; Fake up a combined PC+PSR (PC=0)
AND R1, R0, #I32_bit :OR: F32_bit
AND R0, R0, #&F0000003
ORR R0, R0, R1, LSL #IF32_26Shift
MOV R1, #0
LDR R1, [R1, #ExceptionDump]
STR R0, [R1, #15*4]
]
LDR R0, [R0, -R0]
STR R0, [R1, #1*4]
......
......@@ -95,6 +95,7 @@ Eval_Code ROUT
BL WriteS_Translated_UseR4
= "Result:Result is %0, value :",0
ALIGN
SWI XOS_WriteI + " "
Pull "r4"
]
......@@ -257,6 +258,8 @@ ROMModules_Code ENTRY
ADRGTL r0, rommposp
]
BL %FT21 ; add string
MOV r0, #" "
BL %FT20 ; add space
MOVGT r0, r10 ; if normal podule then use plain number (flags still set from CMP)
MVNLT r0, r10 ; if extension ROM then NOT it (-2 => 1, -3 => 2 etc)
SWINE XOS_ConvertCardinal1
......@@ -343,7 +346,8 @@ ROMModules_Code ENTRY
STRPLB r0, [r1], #1
EXITS
21
EntryS "r0"
EntryS
Push "r0"
MOV r12, r0
22
LDRB r0, [r12], #1
......@@ -355,10 +359,10 @@ ROMModules_Code ENTRY
]
BLNE %BT20
BNE %BT22
PullEnvS
Pull "r0"
SUB r0, r12, r0 ; length of string
SUB r0, r0, #1
MOV pc, lr
EXITS
23
BL %BT20
......
......@@ -1519,11 +1519,6 @@ HexR0Nibble ENTRY "r0"
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
SkipOverNameAndSpaces
Push lr
BL SkipToSpace
Pull lr
SkipSpaces ROUT
10 LDRB r0, [r1], #1
......@@ -1534,15 +1529,15 @@ SkipSpaces ROUT
MOV pc, lr ; r0 = first ~space. Can't really fail
SkipToSpace ENTRY "r0"
SkipToSpace ENTRY
10 LDRB r0, [r1], #1
CMP r0, #&7F
CMPNE r0, #" " ; Leave r1 -> space or CtrlChar
10 LDRB lr, [r1], #1
CMP lr, #&7F
CMPNE lr, #" " ; Leave r1 -> space or CtrlChar
BHI %BT10
SUB r1, r1, #1
CLRV
MOV pc, lr
EXIT
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; In r1 -> string
......
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