Commit 2f224a37 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Misc memory management fixes

Detail:
  s/ChangeDyn - Fix register corruption in PMP_LogOp when mapping a page into a location that already contains a page. Fix excessive TLB flush in AreaShrink.
  s/ARM600, s/VMSAv6 - Add asserts to GetTempUncache to detect invalid register combinations
Admin:
  Tested on BB-xM


Version 5.59. Tagged as 'Kernel-5_59'
parent d181963e
...@@ -11,13 +11,13 @@ ...@@ -11,13 +11,13 @@
GBLS Module_HelpVersion GBLS Module_HelpVersion
GBLS Module_ComponentName GBLS Module_ComponentName
GBLS Module_ComponentPath GBLS Module_ComponentPath
Module_MajorVersion SETS "5.58" Module_MajorVersion SETS "5.59"
Module_Version SETA 558 Module_Version SETA 559
Module_MinorVersion SETS "" Module_MinorVersion SETS ""
Module_Date SETS "23 Aug 2016" Module_Date SETS "07 Sep 2016"
Module_ApplicationDate SETS "23-Aug-16" Module_ApplicationDate SETS "07-Sep-16"
Module_ComponentName SETS "Kernel" Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel" Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.58" Module_FullVersion SETS "5.59"
Module_HelpVersion SETS "5.58 (23 Aug 2016)" Module_HelpVersion SETS "5.59 (07 Sep 2016)"
END END
/* (5.58) /* (5.59)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 5.58 #define Module_MajorVersion_CMHG 5.59
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 23 Aug 2016 #define Module_Date_CMHG 07 Sep 2016
#define Module_MajorVersion "5.58" #define Module_MajorVersion "5.59"
#define Module_Version 558 #define Module_Version 559
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "23 Aug 2016" #define Module_Date "07 Sep 2016"
#define Module_ApplicationDate "23-Aug-16" #define Module_ApplicationDate "07-Sep-16"
#define Module_ComponentName "Kernel" #define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel" #define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.58" #define Module_FullVersion "5.59"
#define Module_HelpVersion "5.58 (23 Aug 2016)" #define Module_HelpVersion "5.59 (07 Sep 2016)"
#define Module_LibraryVersionInfo "5:58" #define Module_LibraryVersionInfo "5:59"
...@@ -21,6 +21,10 @@ DebugAborts SETL {FALSE} ...@@ -21,6 +21,10 @@ DebugAborts SETL {FALSE}
; n.b. temp not used here but included for VMSAv6 compatibility ; n.b. temp not used here but included for VMSAv6 compatibility
MACRO MACRO
GetTempUncache $out, $pageflags, $pcbtrans, $temp GetTempUncache $out, $pageflags, $pcbtrans, $temp
ASSERT $out <> $pageflags ; For consistency with VMSAv6 version
ASSERT $out <> $pcbtrans
ASSERT $out <> $temp ; For consistency with VMSAv6 version
ASSERT $temp <> $pcbtrans ; For consistency with VMSAv6 version
ASSERT DynAreaFlags_CPBits = 7*XCB_P :SHL: 10 ASSERT DynAreaFlags_CPBits = 7*XCB_P :SHL: 10
ASSERT DynAreaFlags_NotCacheable = XCB_NC :SHL: 4 ASSERT DynAreaFlags_NotCacheable = XCB_NC :SHL: 4
ASSERT DynAreaFlags_NotBufferable = XCB_NB :SHL: 4 ASSERT DynAreaFlags_NotBufferable = XCB_NB :SHL: 4
......
...@@ -3069,7 +3069,7 @@ DynArea_PMP_LogOp ROUT ...@@ -3069,7 +3069,7 @@ DynArea_PMP_LogOp ROUT
57 57
; There's already a page at the target address. Unmap it before we ; There's already a page at the target address. Unmap it before we
; replace it (BangCamUpdate isn't smart enough to do this for us) ; replace it (BangCamUpdate isn't smart enough to do this for us)
Push "r2,r4,r6,r7" Push "r2,r4,r6,r7,r10"
LDR r2, =ZeroPage LDR r2, =ZeroPage
LDR r7, [r2, #MaxCamEntry] LDR r7, [r2, #MaxCamEntry]
BL physical_to_ppn BL physical_to_ppn
...@@ -3088,7 +3088,7 @@ DynArea_PMP_LogOp ROUT ...@@ -3088,7 +3088,7 @@ DynArea_PMP_LogOp ROUT
TEQNE r7, #0 TEQNE r7, #0
ORRNE r11, r11, #PageFlags_Unsafe ORRNE r11, r11, #PageFlags_Unsafe
BL BangCamUpdate BL BangCamUpdate
Pull "r2,r4,r6,r7" Pull "r2,r4,r6,r7,r10"
; If the above was unsafe, then it means the below can be unsafe too ; If the above was unsafe, then it means the below can be unsafe too
AND r11, r11, #PageFlags_Unsafe AND r11, r11, #PageFlags_Unsafe
ORR r6, r6, r11 ORR r6, r6, r11
...@@ -4996,7 +4996,7 @@ AreaShrink ROUT ...@@ -4996,7 +4996,7 @@ AreaShrink ROUT
BNE %FT18 BNE %FT18
; Interacting with singly-mapped region - use regular logic ; Interacting with singly-mapped region - use regular logic
MOV r1, r2, LSR #12 MOV r1, r2, LSR #12
ARMop MMU_ChangingUncached,,, r4 ARMop MMU_ChangingUncachedEntries,,, r4
TST r6, #DynAreaFlags_NotCacheable TST r6, #DynAreaFlags_NotCacheable
BNE %FT19 BNE %FT19
LDR r1, [sp] LDR r1, [sp]
......
...@@ -32,6 +32,10 @@ DebugAborts SETL {FALSE} ...@@ -32,6 +32,10 @@ DebugAborts SETL {FALSE}
; Convert given page flags to the equivalent temp uncacheable L2PT flags ; Convert given page flags to the equivalent temp uncacheable L2PT flags
MACRO MACRO
GetTempUncache $out, $pageflags, $pcbtrans, $temp GetTempUncache $out, $pageflags, $pcbtrans, $temp
ASSERT $out <> $pageflags
ASSERT $out <> $pcbtrans
ASSERT $out <> $temp
ASSERT $temp <> $pcbtrans
ASSERT DynAreaFlags_CPBits = 7*XCB_P :SHL: 10 ASSERT DynAreaFlags_CPBits = 7*XCB_P :SHL: 10
ASSERT DynAreaFlags_NotCacheable = XCB_NC :SHL: 4 ASSERT DynAreaFlags_NotCacheable = XCB_NC :SHL: 4
ASSERT DynAreaFlags_NotBufferable = XCB_NB :SHL: 4 ASSERT DynAreaFlags_NotBufferable = XCB_NB :SHL: 4
......
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