Commit 2d883d8d authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Reindent Arthur2.

Expand tabs.
Swap DCI for instructions now Objasm 4 is out.
Symbols for FSControl_CAT/RUN/OPT changed to non Arthur definitions.
Still boots on IOMD class, no other testing.

Version 5.35, 4.79.2.124. Tagged as 'Kernel-5_35-4_79_2_124'
parent 50f95feb
......@@ -21,11 +21,7 @@ Date SETS Module_Date ; Odd-numbered (i.e. development) build, use
; date of last source checkin
|
Date SETS "19 Jan 2010" ; version for RISC OS on desktop computers
; you may also wish to update the welcome
; and OS information dialogue box templates
; in the sources for Desktop and Switcher
; (especially for year change)
; Desktop and Switcher use this via OS_Byte 0
]
]
......
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.123"
Module_Date SETS "26 Nov 2011"
Module_ApplicationDate SETS "26-Nov-11"
Module_MinorVersion SETS "4.79.2.124"
Module_Date SETS "27 Nov 2011"
Module_ApplicationDate SETS "27-Nov-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.123)"
Module_HelpVersion SETS "5.35 (26 Nov 2011) 4.79.2.123"
Module_FullVersion SETS "5.35 (4.79.2.124)"
Module_HelpVersion SETS "5.35 (27 Nov 2011) 4.79.2.124"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.123
#define Module_Date_CMHG 26 Nov 2011
#define Module_MinorVersion_CMHG 4.79.2.124
#define Module_Date_CMHG 27 Nov 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.123"
#define Module_Date "26 Nov 2011"
#define Module_MinorVersion "4.79.2.124"
#define Module_Date "27 Nov 2011"
#define Module_ApplicationDate "26-Nov-11"
#define Module_ApplicationDate "27-Nov-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.123)"
#define Module_HelpVersion "5.35 (26 Nov 2011) 4.79.2.123"
#define Module_FullVersion "5.35 (4.79.2.124)"
#define Module_HelpVersion "5.35 (27 Nov 2011) 4.79.2.124"
#define Module_LibraryVersionInfo "5:35"
......@@ -229,7 +229,7 @@ BangCamUpdate ROUT
ADD r6, r6, r4, LSR #12 ; put back the ones which were too many
ADD r0, r0, r6, LSL #12 ; move on address by the number of pages left
LDMFD r13, {r6} ; reload old logical address
LDR r6, [sp] ; reload old logical address
; now we have r6 = old logical address, r2 = physical page number, r0 = physical address
......
......@@ -621,20 +621,20 @@ Analyse_WB_CR7_Lx
ADRL a1, XCBTableWBR ; assume read-allocate WB/WT cache
STR a1, [v6, #MMU_PCBTrans]
; Enable L2 cache. This could probably be moved earlier on in the boot sequence
; (e.g. when the MMU is turned on), but for now it will go here to reduce the chances
; of stuff breaking
; Enable L2 cache. This could probably be moved earlier on in the boot sequence
; (e.g. when the MMU is turned on), but for now it will go here to reduce the chances
; of stuff breaking
BL Cache_CleanInvalidateAll_WB_CR7_Lx ; Ensure L2 cache is clean
[ M_CortexA9
; write access to ACTLR is only permitted in Secure Mode
; so we must use smc API calls
STMFD sp!, {a2-a4,v3-v4,ip}
LDR ip, =0x102 ; enable/disable PL310 L2 Cache controller
MOV a1, #1 ; enable
myDSB
DCI 0xE1600070 ; SMC #0
LDMFD sp!, {a2-a4,v3-v4,ip}
; write access to ACTLR is only permitted in Secure Mode
; so we must use smc API calls
STMFD sp!, {a2-a4,v3-v4,ip}
LDR ip, =0x102 ; enable/disable PL310 L2 Cache controller
MOV a1, #1 ; enable
myDSB
DCI 0xE1600070 ; SMC #0
LDMFD sp!, {a2-a4,v3-v4,ip}
|
MRC p15, 0, a1, c1, c0, 1
ORR a1, a1, #2 ; L2EN
......@@ -751,7 +751,7 @@ KnownCPUTable
; The cache size data is ignored for ARMv7.
KnownCPUTable_Fancy
CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32, 16, 16K, 32, 16
CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32, 16, 32K, 32, 16
CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32, 16, 32K, 32, 16
CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMv6, WB_CR7_LDa, 1, 16K, 32, 16,16K, 32, 16
DCD -1
......@@ -775,7 +775,7 @@ KnownCPUFlags
DCD CPUFlag_ExtendedPages+CPUFlag_XScale, 0 ; X80200
DCD CPUFlag_XScale, 0 ; X80321
DCD 0, 0 ; Cortex_A8
DCD 0, 0 ; Cortex_A9
DCD 0, 0 ; Cortex_A9
DCD 0, 0 ; ARM1176JZF_S
[ MEMM_Type = "VMSAv6"
......@@ -842,9 +842,9 @@ ARM_Analyse_Fancy
B %FT27
25
; ARMv7 format cache type register.
; This should(!) mean that we have the cache level ID register,
; and all the other ARMv7 cache registers.
; ARMv7 format cache type register.
; This should(!) mean that we have the cache level ID register,
; and all the other ARMv7 cache registers.
; Do we have a split cache?
MRC p15, 1, a1, c0, c0, 1
......@@ -2257,7 +2257,7 @@ PNameTable
DCW PName_X80200 - PNameTable
DCW PName_X80321 - PNameTable
DCW PName_Cortex_A8 - PNameTable
DCW PName_Cortex_A9 - PNameTable
DCW PName_Cortex_A9 - PNameTable
DCW PName_ARM1176JZF_S - PNameTable
PName_ARM600
......@@ -2293,7 +2293,7 @@ PName_X80321
PName_Cortex_A8
= "CortexA8:Cortex-A8 Processor",0
PName_Cortex_A9
= "CortexA9:Cortex-A9 Processor",0
= "CortexA9:Cortex-A9 Processor",0
PName_ARM1176JZF_S
= "ARM1176JZF_S:ARM1176JZF-S Processor",0
ALIGN
......
This diff is collapsed.
......@@ -1064,7 +1064,7 @@ sam001
STRNEB R10, [R10, #MOShasFIQ]
MOVNE r1, #Service_Serviced
fakeservicecall
; do it this way to cope with ARM v4/v3 differences on storing PC
; do it this way to cope with ARM v4/v3 differences on storing PC
SUBEQ stack,stack,#20
STREQ PC,[stack,#16]
BEQ %BT05
......
......@@ -2048,17 +2048,17 @@ CallInit ROUT
STR R4, [R2, #ModSWINode_CallAddress]
STR R11, [R2, #ModSWINode_Number]
ModSWIHashval R3,R11
LDR R4, [R3]
B %FT09
LDR R4, [R3]
B %FT09
; top of loop: R4 = node under consideration, R3 = pointer to this node from previous
08 LDR R14, [R4, #ModSWINode_Number]
TEQ R11, R14 ; if numbers match, jump to end. This also sets
BEQ %FT10 ; the new node's link to this node
ADD R3, R4, #ModSWINode_Link ; update R3 to this node's link
LDR R4, [R3] ; and move R4 to next node
09 TEQ R4, #0
BNE %BT08 ; if no next node, exit loop and tack on new one
10 STR R4, [R2, #ModSWINode_Link]
08 LDR R14, [R4, #ModSWINode_Number]
TEQ R11, R14 ; if numbers match, jump to end. This also sets
BEQ %FT10 ; the new node's link to this node
ADD R3, R4, #ModSWINode_Link ; update R3 to this node's link
LDR R4, [R3] ; and move R4 to next node
09 TEQ R4, #0
BNE %BT08 ; if no next node, exit loop and tack on new one
10 STR R4, [R2, #ModSWINode_Link]
STR R2, [R3]
03 ; now prepared to look at module
......
......@@ -911,7 +911,7 @@ PIRQ_Despatch ; All the same thing now
; TMD 09-Jun-89: Don't corrupt r0 - it's needed by the default IRQ2 routine
LDRB r1, [r1]
EOR r1, r1, r2, LSR #8
EOR r1, r1, r2, LSR #8
ANDS r1, r1, r2
BEQ %BT01
LDMIA r12, {r12, pc}
......
......@@ -710,7 +710,7 @@ OneModule_Failed
UKCNotClaimed
MOV R1, R0
DoFSCV_Run
MOV R0, #FSControl_RUN
MOV R0, #FSControl_Run
71 SWI XOS_FSControl
OscliExit
Pull "R2"
......@@ -751,7 +751,7 @@ OscliExit
Pull "R0, R3-R6"
PercentDot ; entry for *%.
ADD R1, R0, #1
MOV R0, #FSControl_CAT ; *., skip .
MOV R0, #FSControl_Cat ; *., skip .
B %BT71
;***************************************************************************
......
This diff is collapsed.
......@@ -444,7 +444,7 @@ PointerSWI
LDREQB r0, MouseType
BEQ SLVK
[ STB
[ STB
TEQ r0, #2
LDREQB r0, MousePresent
BEQ SLVK
......
......@@ -1035,7 +1035,7 @@ Osbyte8A
; Write Filing System Options : *OPT
Osbyte8B
MOV R0, #FSControl_OPT
MOV R0, #FSControl_Opt
SWI XOS_FSControl
ByteReturnV
......@@ -1125,7 +1125,7 @@ OsbyteA1 ; R1 = address , R2 = result
; Write CMOS RAM
OsbyteA2
CLRPSR I_bit, R0 ; this may take some time
MOVS R0, R1
MOVS R0, R1
[ ProtectStationID
MyOsbyte EQ
]
......
......@@ -349,7 +349,7 @@ PostInit ROUT
;
ResyncTimeSWI
Push "R12,LR"
BYTEWS WsPtr
BYTEWS WsPtr
BL CheckYear ;may have been frozen over new year!
BL RTCToRealTime
Pull "R12,LR"
......
......@@ -1336,7 +1336,7 @@ Load_Code Entry "$UtilRegs"
90 MOVVC r0, #OSFile_Load
[ StrongARM
ORRVC r3, r3, #1<<31
ORRVC r3, r3, #1<<31
]
MOVVC r1, r7 ; Get filename^ back
SWIVC XOS_File
......
......@@ -995,8 +995,8 @@ ramfsarea * 5 ; RAM disc area
vec_fontsize # 4 ; fields in output vector
vec_spritesize # 4
vec_ramfssize # 4
vec_rmasize # 4
vec_screensize # 4
vec_rmasize # 4
vec_screensize # 4
ss_outputvec * &100
Keydef DCB "FontSize/K,SpriteSize/K,RamFSSize/K,RMASize/K,ScreenSize/K"
......
......@@ -327,7 +327,7 @@ VduInit ROUT
LDR R0, [WsPtr, #TotalScreenSize]
RSB R0, R0, R14
STR R0, [WsPtr, #DisplayStart]
BL SetDisplayScreenStart
BL SetDisplayScreenStart
STR R0, [WsPtr, #ScreenStart]
STR R0, [WsPtr, #CursorAddr]
STR R0, [WsPtr, #InputCursorAddr]
......
......@@ -326,7 +326,7 @@ SolidLine ROUT
]
AND R14, R9, R12 ; R14 = zgora AND pixmask
[ AvoidScreenReads
MVNS R11, R14
MVNS R11, R14
LDRNE R11, [R7] ; R11 = word from screen
|
LDR R11, [R7] ; R11 = word from screen
......
......@@ -222,7 +222,7 @@ FlipAboutYAxis ROUT
MOV R10, R9, ROR R11 ; mask for rightmost pixel
Push "R0"
Push "R0"
BL FlipAbY10 ; Now do the mask
Pull "R0"
Pull "R8" ; Retrieve last bit used to find LHwastage
......@@ -321,8 +321,8 @@ RemLHWastage
MOV R7, R6, LSL R14 ; Move LSBs from next word to current
ORR R5, R5, R7
STR R5, [R1],#4 ; store current word
MOV R5, R6 ; move next word to current word ready for
; next loop iteration.
MOV R5, R6 ; move next word to current word ready for
; next loop iteration.
B %BT20
; CMP R2, R1
......
......@@ -369,13 +369,13 @@ SwitchOutputToMask ROUT
BL DefaultWindows
BL Home
90
[ STB ; Change made by TMD 29-May-96, to stop cursor flashing before interlace module has
; fixed up LineLength on Service_SwitchingOutputToSprite
[ STB ; Change made by TMD 29-May-96, to stop cursor flashing before interlace module has
; fixed up LineLength on Service_SwitchingOutputToSprite
MOV R1, #Service_SwitchingOutputToSprite ; issue the service *first*
ADD R2, WsPtr, #VduOutputCurrentState
LDMIA R2, {R2-R5} ; load the registers that were in R0-R3 on entry
IssueService
BL PostWrchCursor ; it should now be safe to restore the cursor
BL PostWrchCursor ; it should now be safe to restore the cursor
|
BL PostWrchCursor
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment