; Copyright 2009 Castle Technology Ltd ; ; Licensed under the Apache License, Version 2.0 (the "License"); ; you may not use this file except in compliance with the License. ; You may obtain a copy of the License at ; ; http://www.apache.org/licenses/LICENSE-2.0 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ; USBTLL registers - relative to L4_USBTLL USBTLL_REVISION * &00 USBTLL_SYSCONFIG * &10 USBTLL_SYSSTATUS * &14 USBTLL_IRQSTATUS * &18 USBTLL_IRQENABLE * &1C TLL_SHARED_CONF * &30 TLL_CHANNEL_CONF_0 * &40 TLL_CHANNEL_CONF_1 * &44 TLL_CHANNEL_CONF_2 * &48 ; ULPI register groups - relative to L4_USBTLL ULPI_BASE * &800 ULPI_SIZE * &100 ULPI_NUM * 2 ULPI_VENDOR_ID_LO * &00 ; All registers are byte sized! ULPI_VENDOR_ID_HI * &01 ULPI_PRODUCT_ID_LO * &02 ULPI_PRODUCT_ID_HI * &03 ULPI_FUNCTION_CTRL * &04 ULPI_FUNCTION_CTRL_SET * &05 ULPI_FUNCTION_CTRL_CLR * &06 ULPI_INTERFACE_CTRL * &07 ULPI_INTERFACE_CTRL_SET * &08 ULPI_INTERFACE_CTRL_CLR * &09 ULPI_OTG_CTRL * &0A ULPI_OTG_CTRL_SET * &0B ULPI_OTG_CTRL_CLR * &0C ULPI_USB_INT_EN_RISE * &0D ULPI_USB_INT_EN_RISE_SET * &0E ULPI_USB_INT_EN_RISE_CLR * &0F ULPI_USB_INT_EN_FALL * &10 ULPI_USB_INT_EN_FALL_SET * &11 ULPI_USB_INT_EN_FALL_CLR * &12 ULPI_USB_INT_STATUS * &13 ULPI_USB_INT_LATCH * &14 ULPI_DEBUG * &15 ULPI_SCRATCH_REGISTER * &16 ULPI_SCRATCH_REGISTER_SET * &17 ULPI_SCRATCH_REGISTER_CLR * &18 ULPI_EXTENDED_SET_ACCESS * &2F ULPI_UTMI_VCONTROL_EN * &30 ULPI_UTMI_VCONTROL_EN_SET * &31 ULPI_UTMI_VCONTROL_EN_CLR * &32 ULPI_UTMI_VCONTROL_STATUS * &33 ULPI_UTMI_VCONTROL_LATCH * &34 ULPI_UTMI_VSTATUS * &35 ULPI_UTMI_VSTATUS_SET * &36 ULPI_UTMI_VSTATUS_CLR * &37 ULPI_USB_INT_LATCH_NOCLR * &38 ULPI_VENDOR_INT_EN * &3B ULPI_VENDOR_INT_EN_SET * &3C ULPI_VENDOR_INT_EN_CLR * &3D ULPI_VENDOR_INT_STATUS * &3E ULPI_VENDOR_INT_LATCH * &3F ; USB host registers - relative to L4_USB_Host UHH_REVISION * &00 UHH_SYSCONFIG * &10 UHH_SYSSTATUS * &14 UHH_HOSTCONFIG * &40 UHH_DEBUG_SCR * &44 OHCI_BASE * &400 EHCI_BASE * &800 ; OHCI registers - relative to OHCI_BASE OHCI_HCREVISION * &00 OHCI_HCCONTROL * &04 OHCI_HCCOMANDSTATUS * &08 OHCI_HCINTERRUPTSTATUS * &0C OHCI_HCINTERRUPTENABLE * &10 OHCI_HCINTERRUPTDISABLE * &14 OHCI_HCHCCA * &18 OHCI_HCPERIODCURRENTED * &1C OHCI_HCCONTROLHEADED * &20 OHCI_HCCONTROLCURRENTED * &24 OHCI_HCBULKHEADED * &28 OHCI_HCBULKCURRENTED * &2C OHCI_HCDONEHEAD * &30 OHCI_HCFMINTERVAL * &34 OHCI_HCFMREMAINING * &38 OHCI_HCFMNUMBER * &3C OHCI_HCPERIODICSTART * &40 OHCI_HCLSTHRESHOLD * &44 OHCI_HCRHDESCRIPTORA * &48 OHCI_HCRHDESCRIPTORB * &4C OHCI_HCRHSTATUS * &50 OHCI_HCRHPORTSTATUS_1 * &54 OHCI_HCRHPORTSTATUS_2 * &58 OHCI_HCRHPORTSTATUS_3 * &5C ; EHCI registers - relative to EHCI_BASE EHCI_HCCAPBASE * &00 EHCI_HCSPARAMS * &04 EHCI_HCCPARAMS * &08 EHCI_USBCMD * &10 EHCI_USBSTS * &14 EHCI_USBINTR * &18 EHCI_FRINDEX * &1C EHCI_CTRLDSSEGMENT * &20 EHCI_PERIODICLISTBASE * &24 EHCI_ASYNCLISTADDR * &28 EHCI_CONFIGFLAG * &50 EHCI_PORTSC_0 * &54 EHCI_PORTSC_1 * &58 EHCI_PORTSC_2 * &5C EHCI_INSNREG00 * &90 EHCI_INSNREG01 * &94 EHCI_INSNREG02 * &98 EHCI_INSNREG03 * &9C EHCI_INSNREG04 * &A0 EHCI_INSNREG05_UTMI * &A4 EHCI_INSNREG05_ULPI * &A4 ; (eh?) END