; Copyright 2013 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;

; SPI registers - relative to L4_McSPI1, L4_McSPI2, etc.
MCSPI_REVISION        * &00
MCSPI_SYSCONFIG       * &10
MCSPI_SYSSTATUS       * &14
MCSPI_IRQSTATUS       * &18
MCSPI_IRQENABLE       * &1C
MCSPI_WAKEUPENABLE    * &20
MCSPI_SYST            * &24
MCSPI_MODULCTRL       * &28
MCSPI_CHxCONF         * &2C
MCSPI_CHxSTAT         * &30
MCSPI_CHxCTRL         * &34
MCSPI_TXx             * &38
MCSPI_RXx             * &3C
MCSPI_XFERLEVEL       * &7C

; Stride between per-channel registers
MCSPI_STRIDE          * &14

; Interrupt numbers
SPI1_IRQ        * 65
SPI2_IRQ        * 66
SPI3_IRQ        * 91
SPI4_IRQ        * 48

        END