diff --git a/VersionASM b/VersionASM index 8a8d07298e047bd79007a6e809c21f41de3d38a8..296ea2eacae76b48afa4ea45807da86bdf7c356a 100644 --- a/VersionASM +++ b/VersionASM @@ -11,13 +11,13 @@ GBLS Module_HelpVersion GBLS Module_ComponentName GBLS Module_ComponentPath -Module_MajorVersion SETS "0.81" -Module_Version SETA 81 +Module_MajorVersion SETS "0.82" +Module_Version SETA 82 Module_MinorVersion SETS "" -Module_Date SETS "30 Sep 2012" -Module_ApplicationDate SETS "30-Sep-12" +Module_Date SETS "08 Oct 2012" +Module_ApplicationDate SETS "08-Oct-12" Module_ComponentName SETS "OMAP3" Module_ComponentPath SETS "castle/RiscOS/Sources/HAL/OMAP3" -Module_FullVersion SETS "0.81" -Module_HelpVersion SETS "0.81 (30 Sep 2012)" +Module_FullVersion SETS "0.82" +Module_HelpVersion SETS "0.82 (08 Oct 2012)" END diff --git a/VersionNum b/VersionNum index 552873fcc7599afcf57d75b3b25caafe5b416352..9d3e2c25e4410be23c3ee4d56618156ae622ef46 100644 --- a/VersionNum +++ b/VersionNum @@ -1,23 +1,23 @@ -/* (0.81) +/* (0.82) * * This file is automatically maintained by srccommit, do not edit manually. * Last processed by srccommit version: 1.1. * */ -#define Module_MajorVersion_CMHG 0.81 +#define Module_MajorVersion_CMHG 0.82 #define Module_MinorVersion_CMHG -#define Module_Date_CMHG 30 Sep 2012 +#define Module_Date_CMHG 08 Oct 2012 -#define Module_MajorVersion "0.81" -#define Module_Version 81 +#define Module_MajorVersion "0.82" +#define Module_Version 82 #define Module_MinorVersion "" -#define Module_Date "30 Sep 2012" +#define Module_Date "08 Oct 2012" -#define Module_ApplicationDate "30-Sep-12" +#define Module_ApplicationDate "08-Oct-12" #define Module_ComponentName "OMAP3" #define Module_ComponentPath "castle/RiscOS/Sources/HAL/OMAP3" -#define Module_FullVersion "0.81" -#define Module_HelpVersion "0.81 (30 Sep 2012)" -#define Module_LibraryVersionInfo "0:81" +#define Module_FullVersion "0.82" +#define Module_HelpVersion "0.82 (08 Oct 2012)" +#define Module_LibraryVersionInfo "0:82" diff --git a/hdr/CPUClk b/hdr/CPUClk index 90f034179fb4375939e38bc50f7d16fb32a00499..4ab5c863749c316879642548423377a278908f77 100644 --- a/hdr/CPUClk +++ b/hdr/CPUClk @@ -31,18 +31,20 @@ OPPTbl_Size # 0 ; Size of each entry OPPTbl_Format * 0 ; Format number as returned by CPUClk_Override -OPPTbl_Max * 18 ; Max number of entries we support (chosen to make us same size as SR driver) +OPPTbl_Max * 17 ; Max number of entries we support (chosen to make us same size as SR driver) ; CPU clock device ^ 0, a1 ; Public bits CPUClkDevice # HALDevice_CPUClk_Size ; Private bits +CPUClkShutdown # 4 ; Pointer to shutdown func. Must be at same offset as SR37xShutdown! CPUClkWorkspace # 4 ; HAL workspace pointer CPUClkNewSpeed # 4 ; Re-entrancy flag. -1 if idle, desired table idx if in process of changing CPU speed. Allows CPUClk_Get to finish changing the speed if it gets called in the middle of a change. CPUClkCurSpeed # 4 ; Current table idx CPUClkOPPTblSize # 4 ; Number of entries in table CPUClkOPPTbl # OPPTbl_Size*OPPTbl_Max ; OPP table +CPUClkOPPDefault # OPPTbl_Size ; Default OPP settings, for shutdown CPUClk_DeviceSize * :INDEX: @ CPUClk_WorkspaceSize * CPUClk_DeviceSize diff --git a/hdr/SR37x b/hdr/SR37x index e4337e3eaff854f54cf3d6c297bc99d6087824cb..df13858f888e266e62df4794708834d33e854ca5 100644 --- a/hdr/SR37x +++ b/hdr/SR37x @@ -86,6 +86,7 @@ SR37x_OPPTbl_Max * 6 ; Max number of entries we support ; Public bits SR37xDevice # HALDevice_CPUClk_Size ; Private bits +SR37xShutdown # 4 ; Pointer to shutdown func. Must be at same offset as CPUClkShutdown! SR37xWorkspace # 4 ; HAL workspace pointer SR37xNewSpeed # 4 ; Re-entrancy flag. -1 if idle, desired table idx if in process of changing CPU speed. Allows SR37x_Get to finish changing the speed if it gets called in the middle of a change. (Note somewhat redundant since SR37x code currently avoids re-entrancy) SR37xCurSpeed # 4 ; Current table idx @@ -99,5 +100,4 @@ SR37x_WorkspaceSize * SR37x_DeviceSize ASSERT SR37x_WorkspaceSize <= CPUClk_WorkspaceSize - END diff --git a/s/Boot b/s/Boot index e763db4a2bba18e110c18331c5d1bcdc03d7fb91..093f9339c245d908ad3fab32804c48f59ee83568 100644 --- a/s/Boot +++ b/s/Boot @@ -62,6 +62,7 @@ MoreDebug SETL Debug :LAND: {FALSE} IMPORT IIC_DoOp_Poll IMPORT CPUClk_PreInit IMPORT CPUClk_Init + IMPORT CPUClk_PreReset ; v8 is used as pointer to RISC OS entry table throughout pre-MMU stage. MACRO @@ -1246,6 +1247,16 @@ HAL_PhysTable DCD 0 HAL_Reset ROUT + Push "a1" + ; Place EHCI PHY in reset + ; This may help unreliable USB on the Pandora following a reset? + LDRB a1, [sb, #BoardConfig_USBGPIO] + MOV a2, #0 + CMP a1, #255 + BLNE GPIOx_SetAsOutput + ; Reset clock speed to default + BL CPUClk_PreReset + Pull "a1" ; Reset or power off? CMP a1, #0 LDREQ pc, [sb, #BoardConfig_PowerOff] diff --git a/s/CPUClk b/s/CPUClk index cca3f20b56b2fa0072c3ecc7963ce821435b2082..fd61a35e7be14ce674a8971d94257b52543fc7f4 100644 --- a/s/CPUClk +++ b/s/CPUClk @@ -33,6 +33,7 @@ EXPORT CPUClk_PreInit EXPORT CPUClk_Init EXPORT CPUClk_AdjustDPLL + EXPORT CPUClk_PreReset IMPORT TPSRead IMPORT TPSWrite @@ -122,11 +123,15 @@ CPUClk_PreInit ROUT ADR a2, CPUClkDevTemplate MOV a3, #HALDevice_CPUClk_Size BL memcpy + ADR a1, CPUClk_Shutdown + STR a1, [v3, #:INDEX: CPUClkShutdown] STR sb, [v3, #:INDEX: CPUClkWorkspace] STR v1, [v3, #:INDEX: CPUClkOPPTblSize] ADD a1, v3, #:INDEX: CPUClkOPPTbl MOV a2, v2 ASSERT OPPTbl_Size = 4 + LDR a3, [v2, v1, LSL #2] ; Get shutdown setting + STR a3, [v3, #:INDEX: CPUClkOPPDefault] MOV a3, v1, LSL #2 BL memcpy ; Poke the last entry in the table if this was a 720MHz model @@ -200,6 +205,14 @@ CPUClk_Init ROUT MOVEQ pc, lr CallOS OS_AddDevice,tailcall +CPUClk_PreReset + ; Call the appropriate shutdown function + ADRL a1, CPUClkWS + LDR a2, CPUClkShutdown + TEQ a2, #0 + MOVNE pc, a2 + MOV pc, lr + MACRO OPPTblEntry $mhz,$vdd1,$clkout_m2 ; VDD1 specified in mV @@ -215,12 +228,14 @@ OPPTbl_OMAP35x OPPTblEntry 550, 1270, 1 ; OPP4 OPPTblEntry 600, 1350, 1 ; OPP5 End_OPPTbl_OMAP35x + OPPTblEntry 500, 1200, 1 ; Shutdown setting: OPP3 @ 1.2V OPPTbl_AMDM37x OPPTblEntry 300, 0970, 2 ; OPP50 OPPTblEntry 600, 1140, 1 ; OPP100 OPPTblEntry 800, 1270, 1 ; OPP130 End_OPPTbl_AMDM37x + OPPTblEntry 600, 1200, 1 ; Shutdown setting: OPP100 @ 1.2V MACRO CPUListEntry $hawkeye, $list @@ -320,6 +335,7 @@ CPUClk_Set ROUT ASSERT OPPTbl_Size = 4 ASSERT OPPTbl_MHz = 0 ADD v2, v2, a2, LSL #2 +10 LDRH v3, [v2, #OPPTbl_MHz] ; a2 = new idx ; v2 = OPP table entry ptr @@ -413,8 +429,15 @@ CPUClk_Set ROUT ADRL a2, CPUClkWS MVN a1, #0 STR a1, [a2, #:INDEX:CPUClkNewSpeed] +90 EXITS ,c +CPUClk_Shutdown ALTENTRY + ; Reset to default speed & voltage prior to reset/power off + ; This avoids Pandora Linux often hanging on boot after RISC OS has been run + myCPSIDi + ADR v2, CPUClkOPPDefault + B %BT10 CPUClk_Override ROUT EntryS diff --git a/s/SR37x b/s/SR37x index f0014659a8b970f2263482ee8a727ff34c318be4..a8a4a90bc2b1b532008ed73404b6892d0c8729ee 100644 --- a/s/SR37x +++ b/s/SR37x @@ -458,6 +458,8 @@ SR37x_PreInit ROUT ADR a2, SR37xDevTemplate MOV a3, #HALDevice_CPUClk_Size BL memcpy + ADRL v1, SR37x_Shutdown + STR v1, [v3, #:INDEX: SR37xShutdown] STR sb, [v3, #:INDEX: SR37xWorkspace] MOV v1, #(End_SR37x_OPPTbl_AMDM37x_VDD1-SR37x_OPPTbl_AMDM37x_VDD1)/SR37x_OPPTbl_Size STR v1, [v3, #:INDEX: SR37xOPPTblSize] @@ -516,6 +518,9 @@ SR37x_OPPTbl_AMDM37x_VDD1 SR37x_OPPTblEntry 1000, 1380, 1, CONTROL_FUSE_OPP1G_VDD1, &fa, &27 ; OPP1G. Note datasheet lists 1.35V as typical voltage, but recommends to use 1.38V instead, to cope with power supply inefficiencies. End_SR37x_OPPTbl_AMDM37x_VDD1 +SR37x_OPPTbl_AMDM37x_VDD1_Default + SR37x_OPPTblEntry 600, 1200, 1, CONTROL_FUSE_OPP100_VDD1, &f9, &16 ; OPP100 @ 1.2V + SR37x_OPPTbl_AMDM37x_VDD2 SR37x_OPPTblEntry 200, 0950, 2, CONTROL_FUSE_OPP50_VDD2, &f4, &0c ; OPP50 SR37x_OPPTblEntry 400, 1140, 1, CONTROL_FUSE_OPP100_VDD2, &f9, &16 ; OPP100 @@ -592,6 +597,7 @@ SR37x_Set ROUT ; a2 = new table index ; Return 0 on success, -1 on failure EntryS "v1-v5,sb" + MOV v1, #0 ; Keep IRQs off for the entireity of the function ; This avoids us having to worry about re-entrancy (which is more complicated than with the CPUClk driver) ; The slowest operation (switching from OPP50 to OPP1G) only takes ~0.343ms, so with the exception of unforseen circumstances (lots of IIC failures in the VC?) we shouldn't have to worry about this hurting our interrupt latency @@ -608,6 +614,7 @@ SR37x_Set ROUT ASSERT SR37x_OPPTbl_MHz = 0 ADD v2, v2, a2, LSL #2 ADD v2, v2, a2, LSL #3 +10 LDRH v3, [v2, #OPPTbl_MHz] ; a2 = new idx ; v2 = OPP table entry ptr @@ -663,6 +670,14 @@ SR37x_Set ROUT MOV a1, #0 EXITS ,c +SR37x_Shutdown ALTENTRY + ; Reset to default speed & voltage prior to reset/power off + ; This avoids Pandora Linux often hanging on boot after RISC OS has been run + ADR v2, SR37x_OPPTbl_AMDM37x_VDD1_Default + MOV v1, #1 ; Exit with smartreflex disabled + CPSID i + B %BT10 + SR37x_Override ROUT EntryS CPSID i @@ -695,6 +710,7 @@ SR37x_Reprogram ROUT Entry "a1-a4,ip" ; Reprogram the SR instance & voltage processor with new values ; In: + ; v1 = nonzero to exit with SR disabled ; v2 = OPPTbl entry ; v4 = voltage processor ; v5 = smartreflex instance @@ -829,6 +845,8 @@ SR37x_Reprogram ROUT BLGT SR37x_Errata146 ; ... and handle errata 1.46 if we've increased voltage ] ; 9. Re-enable modules + CMP v1, #0 + EXIT NE ORR a1, a2, #1 STR a1, [v4, #PRM_VP1_CONFIG] LDR a1, [v5, #SR37x_SRCONFIG]