GitLab

Version 0.93. Tagged as 'HAL_BCM2835-0_93'

* Raspberry Pi 400: verified as booting to desktop.
* Compute Module 3+: some changes to SD support to make it behave like the
  plain Compute Module 3 (previously it was falling into the model B+ code
  path and setting up GPIO in the expectation that an activity LED was
  attached, which is not a given for a Compute Module). Not tested.
* Compute Module 4: tentative support added. Not tested. In particular, we
  don't know what the revision numbers will be yet, so the entries in
  `GPIO_Board_Conversion_Table` may not match real hardware.
* SD subsystem now assumes any future models are similar to the Pi 4 and 400,
  and thus we're more likely that they will "just work" out of the box.

Version 0.92. Tagged as 'HAL_BCM2835-0_92'

Detail:
* Fixes register corruption in GPIOPullDirection.
* Pre-seeds the soft copies with the values from the datasheet (so no need for a function
  to read them). This should also help other models of Pi which assumed they were all
  disabled when it seems they are not!
* Reworks the SDIO driver to call through to the GPIO so that its softcopy is kept in
  sync, and so the settings do something on a Pi 4 at all.
Admin:
  Tested on Pi4 and a Pi 3B+.

Version 0.91. Tagged as 'HAL_BCM2835-0_91'

Version 0.90. Tagged as 'HAL_BCM2835-0_90'

The bridge was incorrectly configured with 2 overlapping mappings (0-&FFFFFFFF and another 0-&8000000). When the VL805 wanted to bus master into main memory the bridge was confused where the transaction should go, causing a master abort to be logged on the secondary side.
Reorganise the PCI memory so that only a small window in the top 1GB is actively decoded (we can't bus master above 3GB anyway due to a chip design "feature"), meaning the rest of the secondary address space is forwarded 1:1 to the primary.
Further, because the CPU side windows can only be sized in powers of 2, reduce that to 2GB in size.

Some Pi 4's - for example, the recently released 8GB variant - don't have the firmware EEPROM on the VL805 fitted. The VideoCore loads default firmware on power on in order to do USB booting, but when RISC OS takes over and does a PCI fundamental reset the VL805 ends up with no firmware running.
Detect this (by peeking the firmware version) and use the NotifyXHCIReset mailbox message to cause the VideoCore to softload the firmware again. Earlier built PCBs *do* contain a firmware EEPROM and skip the mailbox message.

By inspection with a prototype version in BASIC it appears the SCB access needs to be enabled for this to work, it previously wasn't, hence the extra PCI setup step.

Also, reduce the PCI reset delay and rename PCIe_RGR1_SW_INIT1_POWERDOWN to more accurately reflect what it does.

Version 0.89. Tagged as 'HAL_BCM2835-0_89'

The pin list table had the Pi 4-only alternates mixed in, the result of which is that enumerating the pins on something other than Pi 4 would return ghost alternates for peripherals that don't exist.
Split the pin lists and pick the appropriate one.

Also, add 2 missing board revisions that have sneaked out for 2B/3B.

CPUDetect was corrupting the pointer needed for storing the table size

Version 0.88. Tagged as 'HAL_BCM2835-0_88'

Detail:
  The offset to the pull up/down clock register was computed in v4 but then v2 was used instead.

Version 0.87. Tagged as 'HAL_BCM2835-0_87'

From the deep dark recesses of my hard disc, some Pi 1-era test code for
CPU & DMA driven PWM audio, now updated to run on Pi 2, 3, & 4.

Version 0.86. Tagged as 'HAL_BCM2835-0_86'

* Update DMA & DMA lite channels to work on Pi 4 (HAL_IRQClear calls
needed)
* Fix DMAL_Abort / DMAL_Reset to reset the channel properly (register
muddle meant the old reset code wasn't doing anything - and wasn't a
particularly great way of resetting anyway)
* Fix DMAL_CurtailListTransfer not working very well
* Fix IRQ mapping of channels 11-14, allowing channels 12-14 to be used
* Implement support for Pi 4 DMA4 channels. On Pi 4 these are the only
channels we'll bother using, since DMA & DMA lite have annoying
restrictions on accessing RAM above 1GB

The BCM2711 manual suggests that yes, the BCM2835-style memory barriers
are still needed when accessing peripherals

Detail:
  The 8GB model has a new PCB revision too.
Admin:
  Submission from David Pitt.

Version 0.85. Tagged as 'HAL_BCM2835-0_85'

The MAC address when encoded as a Dallas unique id is in network byte order.
For example, a Risc PC returns OS_ReadSysInfo 4 with r0=&A4123456 r1=&0000 because Acorn's EUI is 00:00:A4.

Version 0.84. Tagged as 'HAL_BCM2835-0_84'

The 2GB new minor revision is in the wild.
Also tidy HAL_[Ext]MachineID leftovers.

Version 0.83. Tagged as 'HAL_BCM2835-0_83'

Minor DFM changes resulted in a new revision number
  https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
but only for 4GB.

Give the ISPENDRn address directly, since its only the HAL that knows that iDev_GPU is encoded from 64+, rather than having to bake it into DWCDriver.

The MPHI is (ab)used by DWCDriver as a means to do a FIQ downgrade to IRQ, but Pi 4 has no MPHI, so instead we substitute the GIC (as the GICD_ISPENDRn can be used to cause an IRQ from software).

VCHIQ bulk transfers on Pi 4 use a different page list format, in order
to allow for full use of the larger 36bit physical address space. Add a
flags word to the VCHIQ HAL device so that we can let the VCHIQ module
know what page list format it should use for the machine we're running
on.

The USB controller is at physical addresses outside 32b range, extend so that it can be picked up by PCI manager, and hence use its SWIs (rather than *Memory P) to see registers.
Also write the interrupt number into the config space so it can be picked up.
Requires PCI-0_18.

Memory window now enabled on the VIA VL805, on-chip bridge set to forward memory transactions, ARM CPU to PCI address space translated.
Since we know there's only the VIA chip on the bus, there's no dynamic probing going on like platforms that have PCI sockets. Its BAR settings are derived from defines at the top of PCI.s, so to browse the XHCI capability registers just peek at
  *Memory p 600100000 +20
Only 1 of the 4 address space translation windows is used.

Basic HAL device to expose the GENET peripheral for the driver.

Just enough pokes to be able to scan configuration space such that the VIA XHCI controller can be seen by PCI Manager. Note: at present there are no memory or IO windows open, so you can't (yet) see XHCI registers.

* Requires 'enable_gic=1' in config.txt (or Pi4 dtb to be present?)
* IRQs are managed via the GIC, FIQs via the BCM2838 FIQ controller
* Implemented in s.IntVC6 to avoid making s.Interrupts too
confusing.
* Previous VC6 interrupt support removed from s.Interrupts
* From the OS's perspective, interrupt numbers mostly remain
unchanged. However iDev_QA7 interrupts are unavailable, and some of
the BCM2838 interrupts have been overlaid ontop of them.
* Device drivers must take care to issue HAL_IRQClear, as that is
a new requirement for this HAL

HAL_QueryPlatform was attempting debug output before the debug
UART had been initialised. Since both the PL011 & MiniUART
configuration depends on getting/setting firmware values, fix it
by just removing the debug prints from HAL_QueryPlatform.

RAM sizes above 1GB are not reported by the usual mailbox property, and it
seems unlikely that this will change because the VC RAM allocation has to
remain within the bottom 1GB of the address space (the VC still uses the
upper two bits of its addresses for cache policy) and this property cannot
describe a non-contiguous range. Use the board revision bitfield to recognise
when additional general-purpose RAM exists above the VC allocation. For now,
we're running in "low peripherals" mode, so the top 64MB of 4GB RAM machines
is inaccessible. If the VC allocation is also 64MB, that means the startup
banner of Pi 4 will read 960MB, 1984MB or 3968MB.

Also fix HAL_PhysInfo (and by implication, OS_Memory 6 and 7) to report the
full 35-bit physical address space on Pi 4. The `range` struct filled in by
HAL_PhysInfo has not been extended to 64-bit physical addresses because it
describes RAM, and for now at least, RAM just squeezes into 32-bit addresses.

This controller is now preferred over the legacy EMMC controller, and it is
capable of UHS speeds (pending support in SDIODriver).

Requires RiscOS/Sources/HWSupport/SD/SDIODriver!4

Both still use GIC bypass mode. Assuming for now that extended GPU peripherals
can't support FIQ without GIC (it seems as though they either all use IRQ or
all use FIQ, and RISC OS isn't set up for there being multiple FIQ sources
active at once).

Detail:
* Implement SD activity LED for Pi 4
* Remove inappropriate reprogramming of GPIO47 for Pi 3 B(+) and A+
* Correct the value for SDHCIWriteInterval which is used during SetSDCLK()

Detail:
* Board recognition for Pi 4
* Updated the pin enumeration table to specify new functions available in Pi 4
  (I2C[3456], SPI[3456], UART[2345])

Detail:
* Efforts to get the faster EMMC2 controller working are ongoing. In the
  meantime, this enables the backward-compatible EMMC1 controller.
* The method required to control the activity LED appears to have changed,
  yet again. I haven't worked out how yet, so this is currently
  non-functional.

Detail:
* For now, this uses the legacy interrupt controller, whose register layout has
  unfortunately changed in some unhelpful ways. There is also a GICv2 in the
  SoC, which we will need to transition across to in order to use some of the
  newer peripherals (including USB3 and gigabit Ethernet).
* This requires a corresponding set of changes to start.elf: substitute all
  three instances of &E30011E7 with &E3001000.
* FIQs are not currently supported, as the legacy interrupt controller has
  changed how these are handled. It seems likely that we'll transition to
  GIC before too long, which means it's not worth bothering to implement them
  for the legacy interrupt controller.

Because the mini-UART clock is derived from the core clock, and this varies
by hardware platform and even firmware version, move the initial mailbox
read to before UART initialisation so that this information is available.

Also:
* the IO region previously used only for the QA7 extensions now holds a GIC
  as well on Pi 4, so give it a more generic name
* there's a new, second peripheral IO region to map in as well

The default state for the Serial device (aka OS_SerialOp, and redirection to serial via *FX) is to expect hardware handshaking. However the implementation of HAL_UARTModemStatus when ModemControl = {FALSE} state didn't set a return value so ended up returning a1 = the port number (=0) rather than valid status bits. In turn, DualSerial took that to mean CTS/DSR deasserted and refused to send anything.
To a lesser extent HAL_UARTModemControl also affected, returning a1 = port number 0 too.
For both, set a return value; the value is as though a cable is always present with RTS=CTS and DTR=DSR.

Also, fix the bugs in ModemControl = {TRUE}. This also fakes DTR=DSR which status/control bits don't appear to be implemented in the UART peripheral. Tested briefly, checking CTS state when plugging/unplugging a cable.

Version 0.82. Tagged as 'HAL_BCM2835-0_82'

RISCOS_MapInIO does relatively little processing on the L1PT flags that the
HAL passes to it. However, when modules come along later and try to locate
IO again, using OS_Memory 13, access permissions are specified using a
variation on dynamic area flags. The kernel translates from these to L1PT
flags, and one of the rules it applies is that the shareability bit is set
if on a multiprocessor system. On Pi 2 and later, this means it doesn't find
a match amongst the sections that were mapped in by the HAL, and in practice
this means BCMVideo ends up causing 16MB of IO space to be mapped in twice.

Fix this by passing the L1_S flag to RISCOS_MapInIO on Pi 2 and later. This
effectively frees up an additional 16MB of logical address space for dynamic
areas.

Version 0.81. Tagged as 'HAL_BCM2835-0_81'

On entry to HAL_SendHostMessage, we ensure the contents of the mailbox buffer
are flushed out to the ARM L2 cache (if applicable) and main memory. There
were a couple of instructions to fill in the top two bits of the address
before passing it to the VC, but they were commented out for reasons that are
not clear.

The effect of this is that the VC will look in its L1 and L2 caches for the
data in the buffer. On Pi 1 and 0, this wouldn't be too bad, since ARM11
didn't have its own L2 cache and would have written the data into the VC L2
cache instead, meaning that there would only be coherencency problems if the
VC L1 cache still contained the old contents of the address. On Pi 2-4, it's
more risky, because the VC L2 cache could also be inconsistent with main
memory at this point.

Reinstating the top two bits doesn't appear to cause any ill effects I can
see (tested on Pi 1 and 4), so put these instructions back in.

Version 0.80. Tagged as 'HAL_BCM2835-0_80'

GPIO.s,hdr/BCM2835: Table of known ids updated
SPI.s: Fix long broken compute module support (only the original CM1 would have exported SPI2 due to not checking for the new id scheme).
Unrelated, SDIO.s: Use CallOS macro.

Thanks to Chris Hall for testing this on a CM3+ 8GB model.

Version 0.79. Tagged as 'HAL_BCM2835-0_79'