GitLab

Not tagged

Detail:
  hdr/StaticWS - Reserve workspace for QA7 peripheral address, HAL-wide spinlock, and doorbell device
  Makefile, s/DBell - Add doorbell device implementation
  hdr/BCM2835 - Clean up dead macros, add new macros for spinlock claim/release and basic CPU detection. Define new IRQ numbers for the "QA7" peripheral.
  hdr/CastleMacros, s/Top - Generate two HAL descriptors and entry point tables: One for single-core machines and one for multi-core machines. This avoids some MP-related overheads on ARM11 models of Pi. Implement SMP HAL entry points.
  s/Interrupts - Add support for the QA7 interrupts. Although some interrupts can be flexibly routed to different cores, we currently stick with a static scheme.
  s/Messaging - Use CPUDetect macro
Admin:
  Untested
  Requires Kernel-6_09


Version 0.76. Tagged as 'BCM2835-0_76'

Detail:
  hdr/BCM2835 - Add some new board revision values
  s/SDIO - Treat the 3B+ the same as the 3B when handling the activity LED. Also detect the Embest-manufactured CM1 and treat it the same as the Sony one.
Admin:
  Tested on Raspberry Pi 3B+


Version 0.74. Tagged as 'BCM2835-0_74'

GPOI -> GPIO
set -> cleared
No code change, not tagged.

Detail:
  Move the register accesses for GPIO to the HAL, since they are hardware specific.
  Add recognition of board types for Pi 3, Compute module 3, rev 3 Pi 0's, and the newer Pi 2's with BCM2837 on them.
Admin:
  Based in part on a submission from Tank.
  Tested on a Pi 2. Requires corresponding GPIO module (tag GPIO-1_00-1_11_2_1 or later).

Version 0.67. Tagged as 'BCM2835-0_67'

Detail:
  hdr/BCM2835 - Add switch to allow GPIOs 22-27 to be reconfigured for ARM JTAG access
  s/Top - Configure GPIOs for JTAG if switch enabled
  s/GPIO - Disable GPIO HAL device if JTAG enabled (try and avoid any software messing with the pins)
Admin:
  Tested on Raspberry Pi 1 B, B+


Version 0.66. Tagged as 'BCM2835-0_66'

Detail:
  Look at the reset status register and use the HADPOR flag to influence the OSStartFlag_POR value.
  Fixes problem of OS_Byte 253 always reporting a hard reset, never a power on reset.
Admin:
  Tested on a Pi 2.
  Submission for USB bounty.

Version 0.64. Tagged as 'BCM2835-0_64'

Detail:
  Useful if not just SDIO can see the definitions.

Version 0.62. Tagged as 'BCM2835-0_62'

Detail:
  hdr/BCM2835, hdr/StaticWS, s/Debug, s/Top, s/Video - Fix up the two serial debug switches to work correctly. Disable debug by default.
  s/UART, hdr/UART - Implement HAL UART API, for the PL011 UART.
Admin:
  Tested on Raspberry Pi 1 B
  Requires DualSerial 0.25 to work correctly


Version 0.59. Tagged as 'BCM2835-0_59'

Detail:
  s/Top - On multi-core chips, the ARM boot stub has the other cores sat waiting in a loop near &0. Clearing RAM will inadvertantly break them out of this and most likely cause random crashes later on, so inbetween relocating the ROM and clearing RAM make sure we put the cores into a sleep loop in the HAL. Further mailbox writes can then be used to break them out of this loop, using a similar scheme to that used to break them out of the boot stub loop.
  hdr/BCM2835 - Add some register definitions from the BCM2836 docs
Admin:
  Tested on Pi 2B, 3B
  Not currently dealing with kernel_old=1 case where all cores enter the ROM on startup


Version 0.55. Tagged as 'BCM2835-0_55'

Detail:
  hdr/BCM2835 - Remove mailbox definitions - use the ones exported by BCMSupport to avoid needless duplication
  hdr/StaticWS, s/Messaging, s/Top - Use the mailbox property interface to request & map in the virtual GPIO buffer (if present)
  s/SDIO - On the Pi 3B, the GPIO that was used for the SD activity GPIO is now used for a different purpose. To control the activity LED we need to go via an I2C attached GPIO extender, which itself is exposed to the ARM via the new "virtual GPIO" buffer
  s/VCHIQ - Update to use BCMSupport mailbox definitions
Admin:
  Tested on Pi 1B, 3B


Version 0.54. Tagged as 'BCM2835-0_54'

Detail:
  Makefile, s/Touch - Basic HAL device for the official touchscreen, which just exposes the address of the buffer which the GPU periodically fills with a register dump of the touchscreen controller.
  hdr/BCM2835 - Remove old comment. Add new tag for getting the touchscreen buffer address.
  hdr/StaticWS - Remove old workspace entries. Add new entries for touchscreen.
  s/Messaging - Remove the messagebox tags which set a screen mode on startup (BCMVideo will handle that for us), and just blank the screen instead (to stop the GPU displaying a coloured square). Add tag to get the touchscreen buffer address.
  s/Top - Register touchscreen HAL device during HAL_InitDevices. Remove more old code.
Admin:
  Tested on Raspberry Pi 1 B


Version 0.50. Tagged as 'BCM2835-0_50'

Detail:
  s/SPI - Basic HAL devices for the 3 SPI controllers. These expose the register addresses & IRQ numbers, and (for SPI1 & SPI2) deal with enabling/disabling the hardware and the shared IRQ line. GPIO mapping currently isn't dealt with - we don't know which pin group to use (SPI0 can use two different sets on the compute) or how many chip select lines are desired.
  Makefile - Add SPI source
  hdr/BCM2835 - Add aux SPI registers
  hdr/StaticWS - Reserve workspace for the HAL devices
  s/Top - Register new devices in HAL_InitDevices
Admin:
  Tested on Raspberry Pi B & 2 B


Version 0.45. Tagged as 'BCM2835-0_45'

Detail:
  hdr/BCM2835 - Errata 814220 states that the Cortex-A7 set/way cache maintenance operations violate the usual operation ordering rules, such that an L2 maintenance operation which is started after an L1 operation may actually complete before it, causing data corruption if the L1 data was to be evicted to the L2 entry. Implement the suggested workaround of performing a DSB when switching cache levels, rather than just at the end of the combined L1+L2 group of operations.
  Also, fix missing 99 label that would have caused a stack imbalance in the unlikely event of encountering a processor with fully coherent caches
Admin:
  Tested on Raspberry Pi 2


Version 0.43. Tagged as 'BCM2835-0_43'

Detail:
  * Compute module support consists of eMMC support in the SDHCI driver. The
    eMMC chip on the Compute module only works reliably if under-clocked to
    25 MHz.
  * Pi 1 vs Pi 2 differences are selected at runtime by checking the CPU ID,
    so a single ROM image will work with both boards.
  * Added ARMv7 cache maintenance routine for use on Pi 2.
  * The physical address of the peripherals has moved in Pi 2 to make space
    for the 1 GB of RAM.
  * The ARM physical address space is mapped differently onto the GPU
    address space in Pi 2 because the ARM now uses the L2 cache that comes
    with the Cortex-A7 instead of the GPU's L2 cache.
  * Still waiting for confirmation on the board revision ID that will be
    used for Pi 2, so may require further tweaks for production releases.


Version 0.40. Tagged as 'BCM2835-0_40'

Detail:
  hdr/BCM2835, hdr/USB, s/USB - Update HAL_USBControllerInfo to return the MPHI address & IRQ number
  s/Interrupts - Add some missing memory barriers. Change FIQ enable/disable calls to not alter IRQ masking of the interrupt - simplifies the code and avoids any ordering issues with code that switches interrupts between IRQ & FIQ
  s/Timers - Add missing memory barrier
Admin:
  Tested on Raspberry Pi
  Requires Kernel-5_35-4_79_2_227 to build


Version 0.34. Tagged as 'BCM2835-0_34'

Detail:
  hdr/BCM2835 - Add definition for highest IRQ number
  s/Boot, s/Interrupts - Added HAL_IRQMax implementation, to ensure correct functionality with latest Kernel
Admin:
  Tested on 256MB Pi model B
  Requires Kernel-5_35-4_79_2_182


Version 0.29. Tagged as 'BCM2835-0_29'

Detail:
  hdr/StaticWS, s/Top, s/Video - Added a simple VDU HAL device that exposes a DMA channel to BCMVideo for use with GraphicsV_Render
  hdr/BCM2835 - Don't allow DMA channel 12 to be used; latest firmware seems to have a bug which claims its free when in reality it isn't.
  s/Messaging, s/DMA - Adjust DMA init to allow the video device to claim a DMA channel before the DMA devices are initialised
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.25. Tagged as 'BCM2835-0_25'

Detail:
  hdr/BCM2835, hdr/StaticWS, s/IIC - On rev 2 boards the usage of BSC0 and BSC1 have been swapped, such that BSC1 is now sent to the expansion header instead of BSC0.
  To allow RISC OS to continue to work with clock chips and other hardware fitted to the header, expose BSC1 to RISC OS if on a rev 2 board, or BSC0 if on a rev 1.
Admin:
  Changes received from Dave Higton
  Tested by Dave on rev 1 & rev 2 boards, with IIC devices
  Tested by me on rev 1 board (with no IIC devices fitted)


Version 0.24. Tagged as 'BCM2835-0_24'

Detail:
  Makefile, s/Display - Deleted on-screen debug code
  hdr/BCM2835, hdr/StaticWS, s/IIC, s/Messaging, s/Stubs, s/Top, s/UART - Strip out calls to on-screen debug code, and a few bits of video code
  s/Video - Video code removed and replaced with stub functions similar to other HALs. Only remaining useful code is HAL_Video_StartupMode, which in time should probably be moved to BCMVideo as well.
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.21. Tagged as 'BCM2835-0_21'

Detail:
  Implementation of the high-level HAL IIC interface provided by Dave Higton.
Admin:
  Checked it builds and runs at ROOL.

Version 0.20. Tagged as 'BCM2835-0_20'

Add GPIO & VCHIQ HAL devices. Fix FlushDataCache macro to perform a clean & invalidate instead of just an invalidate.

Detail:
  s/GPIO - Basic implementation of the GPIO HAL device to allow the GPIO module to detect the board type
  s/VCHIQ, hdr/StaticWS - New VCHIQ HAL device which exposes the functionality required by the work-in-progress VCHIQ driver.
  Makefile, s/Top - Hook up the new files/devices
  hdr/BCM2835 - Make the FlushDataCache macro perform a clean & invalidate, to match the behaviour of FlushDataCacheRange
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.17. Tagged as 'BCM2835-0_17'

        HAL_MachineID functioning correctly
Admin:


Version 0.15. Tagged as 'BCM2835-0_15'

Detail:
	HAL_Reset now causes a complete reboot of the machiine. It isnt yet properly called from
	the kernel.. I've not investigated why yet. Behaviour tested using OS_Hardware call

	HAL_MachineID, with the github start.elf from 18 July 2012 will provide a valid MAC address ..
	i.e. that specific to this machine. The a1 value in HAL_ExtendedID needs to be set 0 for this to be reported
	by OS_ReadSysInfo .. unfortunately, again at this stage, it stalls the boot when set 0, so just for now
	the committed value for a1 in HAL_ExtendedID is not 0 .

	centralised messaging routine added. This is used a fair bit in acquiring the operating environment
	Not yet used in the DMA stuff. probably ought to be. At present the messaging channel this mainly
	handles is not complete, so information from this code is still WIP

Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.14. Tagged as 'BCM2835-0_14'

Detail:
  s/DMA, hdr/DMA, Makefile - DMA driver, as an implementation of the DMA controller and list type DMA channel HAL devices
  hdr/StaticWS - Added DMA workspace definition
  hdr/BCM2835 - Removed DMA control block definition (now in hdr/DMA). Add definitions for the mailbox property interface, which should be supported by the GPU firmware sometime soon.
  s/Top - Export a couple of the debug functions. Store logical & physical address of NCNB workspace instead of hackily getting phys addr of the (cacheable) HAL workspace. Call DMA_InitDevices in HAL_InitDevices.
Admin:
  Tested in BCM2835 ROM
  DMA driver hasn't received large amounts of testing, lacks support for finite-length circular transfers, and currently only has one DMA channel enabled
  More DMA channels should be available once the mailbox property interface is functional and we know which channels the GPU does and doesn't use.


Version 0.11. Tagged as 'BCM2835-0_11'

Detail:
  hdr/USB - New header with definition of usbinfo struct that's used by HAL_USBControllerInfo
  hdr/BCM2835 - Add note clarifying how mailboxes are used
  s/Top - Enable power to USB on startup
  s/USB - Implement HAL_USBControllerInfo to expose Synopsys USB controller details to RISC OS
Admin:
  Tested in BCM2835 ROM with Apr 19th start.elf


Version 0.07. Tagged as 'BCM2835-0_07'

Detail:
  Substituted remaining hard spaces with normal ones and expanded tabs.
  This now matches the de facto standard for other components, and also looks
  better in the CVS web viewer.
Admin:
  No code changes

Version 0.06. Tagged as 'BCM2835-0_06'

Detail:
 * Moved interrupt and timer code out of s.Stubs - they're not stubs any more.
 * Rewrote timer and counter code to use GPU system timer 1 for our Timer0
   rather than the ARM timer. This is recommended in the Broadcom datasheet
   because it's driven from the APB clock and so its speed will vary in
   reduced or low power mode.
 * HAL_CounterDelay now, well, does a delay!
 * Added a Timer1, driven from GPU system timer 3 - common code with Timer0.
 * Reshuffled device numbers so the GPU interrupts are at the bottom. This
   works better for FIQs and makes Timer0 the lowest priority interrupt.
 * Higher device numbers are now consistently treated as higher priority.
 * Stopped using bits 8-31 of the basic interrupt registers. These can't be
   masked, so they cause the kernel to lock up if generated, which happens
   if the GPU interrupt which they alias is generated (which appears to
   include the timers even though this is not documented).
 * Added definitions for all the interrupts, including those redacted from the
   datasheet - we need them at least for timers, USB and SD.
 * Stopped HAL_IRQClear from doing anything - this interrupt controller
   doesn't do latching. To acknowledge timer interrupts, you should use
   HAL_TimerIRQClear (and HAL_IRQClear too for compatibility with other ports).
 * Implemented HAL_IRQStatus and all the FIQ control routines.
 * Offsets to interrupt controller registers now use symbolic names.
 * Replaced some hard spaces in sources with normal ones.
Admin:
  Tested on a beta Raspberry Pi. Confirmed that interrupt handlers for both
  ARM and GPU sources can both be operational simultaneuosly. However, the FIQ
  code has not been tested. Timer0 is verified as running at the correct
  speed and reporting a count *down* in the correct range (not a count up as
  some previous versions did). HAL_CounterDelay appears correct also.

Version 0.04. Tagged as 'BCM2835-0_04'

Detail:
   Recent changes in the broadcom startup code now accomodated. frame buffer
   will now determine whether it is L2 cached or not, and be set up accordingly.
   ATAGs not currently read, so ram size defaulted.
  ** note that there will be further updates to this over the following days
  ** trackikng startup code changes.
   added HAL_TimerIRQClear entry
Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.03. Tagged as 'BCM2835-0_03'

  Will now compile against initial developemnt start.elf, and against the
  start.elf in general release at this date. (compile switch UseALBlob in
  hdr.BCM2835). Extended header defs, Updated IRQ stuff, HAL_FramebufferAddress
  Reworked Timers, + a number of other bits. Still work in progress.
Detail:
  (list files and functions that have changed)
Admin:
  Compiled and working - as far as it goes -. Will enable use with the current
  start.elf, and is (subject to any minor changes introduced) ready for use with the
  version due for release shortly which will provide the correct transparency operation,
  and a better aligned frame buffer

Version 0.02. Tagged as 'BCM2835-0_02'

Detail:
  Covers the basic functionality, but does require a customised start.elf
  to function. The vast majority is an entirely new implementation and is
  BSD licenced, but 4% (the Makefile and a handful of simple macros) are
  copied from pre-existing Castle-licenced code, so it lives under the
  "mixed" hierarchy. If other HALs are anything to go by, we'll end up
  having to add more Castle code (at least some C runtime functions) so it's
  probably juast as well.
Admin:
  Code received from Adrian Lees