Commit ef241880 authored by John Ballance's avatar John Ballance
Browse files

Various updates to do with the messaging channel, HAL_MachineID, and HAL_Reset

Detail:
	HAL_Reset now causes a complete reboot of the machiine. It isnt yet properly called from
	the kernel.. I've not investigated why yet. Behaviour tested using OS_Hardware call

	HAL_MachineID, with the github start.elf from 18 July 2012 will provide a valid MAC address ..
	i.e. that specific to this machine. The a1 value in HAL_ExtendedID needs to be set 0 for this to be reported
	by OS_ReadSysInfo .. unfortunately, again at this stage, it stalls the boot when set 0, so just for now
	the committed value for a1 in HAL_ExtendedID is not 0 .

	centralised messaging routine added. This is used a fair bit in acquiring the operating environment
	Not yet used in the DMA stuff. probably ought to be. At present the messaging channel this mainly
	handles is not complete, so information from this code is still WIP

Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.14. Tagged as 'BCM2835-0_14'
parent d05a29d9
......@@ -17,7 +17,7 @@
COMPONENT = BCM2835 HAL
TARGET = BCM2835
OBJS = Top CLib CMOS Debug Display Interrupts SDIO Stubs Timers UART USB Video DMA
OBJS = Top CLib CMOS Debug Display Interrupts SDIO Stubs Timers UART USB Video DMA Messaging
HDRS =
CMHGFILE =
......
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.13"
Module_Version SETA 13
Module_MajorVersion SETS "0.14"
Module_Version SETA 14
Module_MinorVersion SETS ""
Module_Date SETS "17 Jul 2012"
Module_ApplicationDate SETS "17-Jul-12"
Module_Date SETS "19 Jul 2012"
Module_ApplicationDate SETS "19-Jul-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.13"
Module_HelpVersion SETS "0.13 (17 Jul 2012)"
Module_FullVersion SETS "0.14"
Module_HelpVersion SETS "0.14 (19 Jul 2012)"
END
/* (0.13)
/* (0.14)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.13
#define Module_MajorVersion_CMHG 0.14
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 17 Jul 2012
#define Module_Date_CMHG 19 Jul 2012
#define Module_MajorVersion "0.13"
#define Module_Version 13
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MinorVersion ""
#define Module_Date "17 Jul 2012"
#define Module_Date "19 Jul 2012"
#define Module_ApplicationDate "17-Jul-12"
#define Module_ApplicationDate "19-Jul-12"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.13"
#define Module_HelpVersion "0.13 (17 Jul 2012)"
#define Module_LibraryVersionInfo "0:13"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (19 Jul 2012)"
#define Module_LibraryVersionInfo "0:14"
......@@ -44,10 +44,6 @@ HALDebug SETL {TRUE}
GBLL ExtFramestore
ExtFramestore SETL {TRUE}
; set TRUE if using the start.elf originally used for development. FALSE otherwise
GBLL UseALBlob
UseALBlob SETL {FALSE}
GBLL SCR32
SCR32 SETL {TRUE}
......@@ -82,13 +78,8 @@ Debug SETL {TRUE}
;ROM_Base * &00000000
[ UseALBlob
IO_Base * &08000000
IO_Size * &00c00000
|
IO_Base * &20000000
IO_Size * &01000000
]
RAM_Base * &00000000 ; try off bottom
Boot_RAM_Base * &00000000
DMA_RAM_Base * &C0000000 ; base physical address of ram for DMA purposes
......@@ -98,20 +89,6 @@ GPU_L2CnonAl * &40000000 ; GPU L2 cached non allocating coher
GPU_L1L2Cac * &00000000 ; both L1 and L2 cached GPU side
GPU_CacheMask * &c0000000
[ UseALBlob
; FB_MemBase is the point at which riscos is 'capped'
; valid megabyte boundaries at &1e00000, &1f00000 and &2000000
; FB_Address is the start address of the frame buffer. Valid addresses
; (ideally) anywhere between &1e00000 and &2000000
; FB_Length is max framebuffer length. &800000 is just more than
; required for a 1920*1080 32bpp screen
; conclusions .. at the moment the wimp system/desktop appears to need megabyte ; base alignment
FB_MemBase * &01e00000 ; top address of our memory
FB_Address * &01e00000;&01f90000;&01f83ea0;
FB_Length * &007f8000;&00800000;
ASSERT FB_MemBase <= FB_Address
|
]
;
; Timer details
;
......@@ -311,7 +288,7 @@ ARM2VC_Tag_FBSetPalette * &0004800b ; do ranged update of table
; mem barrier operation; ensures all explicit mem operations completed before
; instruction exits.
; (value 4 is all insructions, value 5 is just mem instructions)
; (value 4 is all instructions, value 5 is just mem instructions)
; zeroes $r
MACRO
$label DataSyncBarrier $r, $cond
......@@ -448,6 +425,19 @@ DMA_CH_Count * 13 ; Allegedly 16 channels, but can only get IRQs from 13
;
PM_Base * &00100000 ; power management
PM_Rstc * &1c ; reset control reg
PM_Rsts * &20 ; reset status reg (?)
PM_Wdog * &24 ; watchdog control reg
; register bits
PM_Wdog_Reset * &00 ; watchdog reset
PM_Password * &5a000000
PM_Wdog_TimeSet * &000fffff
PM_Rst_WCfgClr * &ffffffcf
PM_Rst_WCfgSet * &00000030
PM_Rst_WCfg_FullRst * &00000020
PM_Rst_Reset * &00000102
;
;
USB_Base * &00980000 ; USB
ISP_Base * &00a00000 ; ISP
;
......
......@@ -71,6 +71,7 @@ IRQ_Base_Address # 4
ARM_Counter_IO_Address # 4
ARM_Timer_IO_Address # 4
UARTFCRSoftCopy # 4
MMUOffBaseAddr # 4 ; original address kernel was loaded from
Timer SETA 0
WHILE Timer < NumTimers
......@@ -81,6 +82,16 @@ Timer SETA Timer + 1
FB_Base # 4
FB_Size # 4
FB_CacheMode # 4
; info interrogated from the VC side
VC_Memory # 4
ARM_Memory # 4
; align to 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
! 0,"tagbuffer at ":CC::STR:(&fc001000+:INDEX:@),0
tagbuffer # 256 ;; for now ; platform query buffer
; align to 16 byte boundary
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
mbram # 0 ; structure needed for frame buffer descriptor
......
;
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, John Ballance
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
;
AREA |ARM$$code|, CODE, READONLY, PIC
GET Hdr:ListOpts
GET hdr.BCM2835
GET hdr.StaticWS
IMPORT workspace
[ HALDebug
IMPORT output_hex8
IMPORT output_newline
IMPORT output_text
IMPORT output_text_at
IMPORT HAL_DebugHexTX4
IMPORT HAL_DebugTXStrInline
]
EXPORT HAL_SendHostMessage
EXPORT HAL_QueryPlatform
EXPORT MacAdd
EXPORT RamAd
EXPORT SerNo
EXPORT Displ
; send a message packet to the host and await the reply
; on entry, r0 = message channel to use and/or wholemessage
; r1 -> message tag buffer, 16 byte aligned. or 0
;
; on exit, r0 = mailbox response word
;
HAL_SendHostMessage ROUT
STMFD r13!, {r1-r3, lr}
DoMemBarrier r3
FlushDataCache r3
LDR r3, PeriBase
ADD r3, r3, #MB_Base
; check we can send a message
001 LDR r2,[r3, #MB_Sta]
TST r2, #MB_Sta_Full
BNE %BT001 ; write channel full
; send message
TEQ r1, #0
BICNE r1, r1, #&c0000000
; LDRNE r2, FB_CacheMode
; ORRNE r1, r1, r2
ORR r2, r0, r1
AND r1, r0, #&f ; isolate channel number
STR r2,[r3, #MB_ChWr]
; await response and check it is ours
002 LDR r0,[r3, #MB_Sta]
TST r0, #MB_Sta_Empty
BNE %BT002 ; still empty
LDR r0,[r3,#MB_ChRd]
AND r2, r0, #&f
CMP r2, r1 ; check its is our channel
BNE %BT002 ; not our reply
DoMemBarrier r3
LDMFD r13!, {r1-r3, pc} ; returning composite response in r0
; Interrogate the platform and set up basic machine
; Sets up L2 cache addressing mode
; ARM_Memory_MB (in Megabytes)
; Frame buffer base address for 32bit fb
; Board_MAC address
; Board_Serial
;
HAL_QueryPlatform ROUT
STMFD R13!, {r0-r5, lr}
[ HALDebug
bl HAL_DebugTXStrInline
DCB "HalQueryPl",10,0
ALIGN
]
adrl r1, tagbuffer
adr r0, tagb
mov r2, #tagslen
lp1 ldr r3, [r0], #4
str r3, [r1], #4
subs r2, r2, #4
bgt lp1
mov r4, #&40000000 ; L2 Cache off mode
str r4, FB_CacheMode
adrl r1, tagbuffer
MOV r0, #MB_Chan_ARM2VC
BL HAL_SendHostMessage
ADRL r0, tagbuffer
add r0,r0,#Dispbs-tagb
LDR r0, [r0]
; LDR r0, Dispbs
[ HALDebug
bl HAL_DebugHexTX4
]
STR r0, FB_Base
ADRL r0, tagbuffer
add r0, r0,#:INDEX:Dispsz-:INDEX:tagb
LDR r0, [r0]
; LDR r0, Dispsz
[ HALDebug
bl HAL_DebugHexTX4
]
[ HALDebug
bl HAL_DebugTXStrInline
DCB "HalQueryPldone",10,0
ALIGN
]
LDMFD R13!, {r0-r5, pc}
EXPORT MacAdd
EXPORT RamAd
EXPORT SerNo
EXPORT Displ
MacAdd DCD :INDEX:MAClo - :INDEX:tagb + :INDEX:tagbuffer
RamAd DCD :INDEX:ARMbs - :INDEX:tagb + :INDEX:tagbuffer
SerNo DCD :INDEX:SNlo - :INDEX:tagb + :INDEX:tagbuffer
Displ DCD :INDEX:Dispbs - :INDEX:tagb + :INDEX:tagbuffer
; series of VC side query tags. Using inline code as this is writable at this
; stage. This means the answers will be encapsulated in rom image!!
;
; CURRENT ASSIGNED SPACE 256 bytes.. BEWARE
;
tagb DCD tagslen
DCD 0
tagmac DCD ARM2VC_Tag_GetBoardMAC
DCD 8
DCD 0
MAClo DCD 0
MAChi DCD 0
tagserial
DCD ARM2VC_Tag_GetBoardSerial
DCD 8
DCD 0
SNlo DCD 0
SNhi DCD 0
tagarmmem
DCD ARM2VC_Tag_GetARMMemory
DCD 8
DCD 0
ARMbs DCD 0
ARMsz DCD 0
tagvcmem
DCD ARM2VC_Tag_GetVCMemory
DCD 8
DCD 0
VCbs DCD 0
VCsz DCD 0
tagdisplphyswh
DCD ARM2VC_Tag_FBSetPhysDimension
DCD 8
DCD 8
DCD 1920
DCD 1080
tagdisplvirtwh
DCD ARM2VC_Tag_FBSetVirtDimension
DCD 8
DCD 8
DCD 1920
DCD 1080
tagdisplvirtoffset
DCD ARM2VC_Tag_FBSetVirtOffset
DCD 8
DCD 8
DCD 0
DCD 0
tagdispldepth
DCD ARM2VC_Tag_FBSetDepth
DCD 4
DCD 4
DCD 32 ; 32bit
tagdisplpixord
DCD ARM2VC_Tag_FBSetPixelOrder
DCD 4
DCD 4
DCD 1 ; RGB
tagdisplalpha
DCD ARM2VC_Tag_FBSetAlphaMode
DCD 4
DCD 4
DCD 2 ; channel 1=alpha reversed 2=ignore
taggetpitch
DCD ARM2VC_Tag_FBGetPitch
DCD 4
DCD 0
DCD 0
tagdisplalloc
DCD ARM2VC_Tag_FBAlloc
DCD 8
DCD 8
Dispbs DCD 0x100000 ; megabyte aligned
Dispsz DCD 0
DCD ARM2VC_Tag_End
tagslen * . - tagb
END
......@@ -145,7 +145,15 @@
IMPORT DMA_InitDevices
IMPORT HAL_SendHostMessage
IMPORT HAL_QueryPlatform
EXPORT HAL_Base
IMPORT MacAdd
IMPORT RamAd
IMPORT SerNo
IMPORT Displ
HAL_Base
[ HALDebug
......@@ -292,43 +300,28 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
ADRL sb,workspace
ADRL R13,end_stack
[ HALDebug
ADRL r4, reset
STR r4, MMUOffBaseAddr
LDR r4,=IO_Base
STR r4,PeriBase
[ HALDebug
mov a1, #1
bl HAL_UARTStartUp ; start early for debug use
bl HAL_DebugTXStrInline
DCB "HalStartup",10,0
ALIGN
]
LDR R4,mbox_addr
; Enable USB power
; Note - may need changing to enable other devices in future
; Looks like we need to write the logical OR of all the devices we want enabled
LDR r3,=(16:SHL:MB_Pwr_USB)+MB_Chan_Pwr
STR r3,[r4,#MB_ChWr]
09
LDR r1,[r4,#MB_Sta]
TST r1,#MB_Sta_Empty
BNE %BT09
LDR r0,[r4,#MB_ChRd]
CMP r0,r3
BNE %BT09
[ UseALBlob
; For now, just assume that we have 40MB of memory...
; set frame buffer at the top...1920x1080x32bpp requires 8MB
LDR R1,=FB_Length
STR R1, FB_Size
LDR R1,=FB_Address
STR R1, FB_Base
ORR R3,R1,#DMA_RAM_Base + MB_Chan_FB
STR R3,[R4,#MB_ChWr]
and r0, r3, #GPU_CacheMask
str r0, FB_CacheMode
|
MOV r1, #0
LDR r0,=(16:SHL:MB_Pwr_USB)+MB_Chan_Pwr
BL HAL_SendHostMessage
BL HAL_QueryPlatform
ldr r1, =1920
str r1, mbxres
str r1, mbxvres
......@@ -341,44 +334,41 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
MOV r1, #16
]
str r1, mbbpp
ADR r1, mbram
ORR R3, R1, #GPU_L2CnonAl + MB_Chan_FB; try with L2 cache on
10 str r3, [r4, #MB_ChWr]
11 ldr r0, [r4, #MB_Sta] ; await response
tst r0, #MB_Sta_Empty
bne %bt11
ldr r0, [r4, #MB_ChRd]
teq r0, #MB_Chan_FB
bne %bt11 ; not the response to our request
ldr r1, mbscrsz
str r1, FB_Size
mov r0,r1
ADD R4, R4, #MB_Base
ADR R0, mbram
ORR R2, R0, #GPU_L2CnonAl + MB_Chan_FB; try with L2 cache on
MOV R0, R2
10
MOV r1, #0
BL HAL_SendHostMessage
ldr r3, mbscrsz
str r3, FB_Size
mov r0,r3
bl HAL_DebugHexTX4
ldr r1, mbbase
and r0, r1, #GPU_CacheMask
str r0, FB_CacheMode
ldr r3, mbbase
and r1, r3, #GPU_CacheMask
str r1, FB_CacheMode
bl HAL_DebugHexTX4
teq r1, #0 ;did we get an answer
ORREQ R3, R3, #GPU_UnCached + MB_Chan_FB; try with L2 cache off
BEQ %BT10 ; 0 size.. try with L2 off
bic r1, r1, #GPU_CacheMask
str r1, FB_Base
mov r0,r1
bic r3, r3, #GPU_CacheMask
str r3, FB_Base
mov r0,r3
bl HAL_DebugHexTX4
]
[ HALDebug
[ SCR32
LDR R0,=1920*8*4
STR R1,ScreenBase ; for HAL use, remember address we were given
STR R3,ScreenBase ; for HAL use, remember address we were given
STR R0,BytesPerRow
MOV R0,#8*4
STR R0,BytesPerChar
|
LDR R0,=1920*8*2
STR R1,ScreenBase
STR R3,ScreenBase
STR R0,BytesPerRow
MOV R0,#8*2
STR R0,BytesPerChar
......@@ -432,41 +422,25 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
ALIGN
]
]
[ UseALBlob ; nolonger used
; Traverse list of 'atags' structures
; word 0 = size of tag, including header, in words
; word 1 = type tag
ATAG_MEM * &54410002
ATAG_NONE * 0
ADRL v1, HAL_Base + OSROM_HALSize
LDR v2, [v1, #OSHdr_ImageSize]
ADD v2, v2, v1 ; End of OS
ADRL v3, atags
atags_loop
LDR a1, [v3, #4] ;tag type
LDR a2, [v3] ;size of tag inc header, in words
SUB a4, a1, #ATAG_MEM :AND: &FF000000
SUB a4, a4, #ATAG_MEM :AND: &00FF0000
TEQ a4, #ATAG_MEM :AND: &FFFF
BNE atag_next
; clear RAM
LDR a1, [v3, #8] ;RAM size
LDR lr, [v3, #12] ;RAM start
[ UseALBlob
;!!! bodge to exclude frame buffer
LDR a3, =FB_MemBase
CMP a1, a3
MOVHI a1, a3
STRHI a1, [v3, #8]
ROMTOP * 6 <<20
RAMTOP * 128 <<20
ADRL a3, workspace
ADRL lr,RamAd
LDR lr, [lr]
ADD a3, a3, lr
LDMIA a3, {a1, a2}
[ HALDebug
bl HAL_DebugHexTX4 ; ram start
mov a1, a2
bl HAL_DebugHexTX4 ; ram end
mov a1, a3
bl HAL_DebugHexTX4 ; ram end
LDMIA a3, {a1, a2}
]
; debug hack to force 128meg ram and 6meg rom
MOV v2, #ROMTOP ;start of available RAM, after HAL + OS image
MOV a1, #RAMTOP ; end of RAM
MOV a2, #0
MOV a3, #0
MOV a4, #0
......@@ -474,7 +448,6 @@ atags_loop
MOV v5, #0
MOV v7, #0
MOV ip, #0
ADD a1, a1, lr ;end of RAM
MOV lr, #0
clear_lp
......@@ -484,15 +457,9 @@ clear_lp
STMDB a1!,{a2-a4,v4,v5,v7,ip,lr}
CMP a1, v2
BHI clear_lp
;!!! this assumes single call :)
LDR lr, [v3] ;tag size, words
LDR v1, [v3, #8] ;RAM size
LDR a4, [v3, #12] ;RAM start
MOV a2, v2 ;start of available RAM, after HAL + OS image
ADD a3, v1, a4 ;end of RAM
ADD v3, v3, lr, LSL #2 ;next tag
mov a2, v2
ADD a3, a2, #RAMTOP ; end of RAM
SUB a3, a3, #ROMTOP ; less what is used
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
......@@ -504,210 +471,13 @@ clear_lp
STR a1,[sp] ;ref for next call
B atags_loop
atag_next
TEQ a1,#ATAG_NONE
ADDNE v3, v3, a2, LSL #2
BNE atags_loop
|
; Determine how much RAM we have available
[ {FALSE} ; Below code believed to work OK with a test start.elf, but need to retest with a release version to be sure
MOV v7, sp
BIC sp, sp, #31
SUB sp, sp, #32
MOV a1, sp ; buffer for mailbox message
MOV a2, #32
MOV a3, #0
LDR a4, =ARM2VC_Tag_GetARMMemory
MOV v1, #8 ; Assume only 1 RAM block (8 byte response buffer)
MOV v2, #0
MOV v3, #0
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