Commit a86bcb4d authored by Committed by ROOLBrowse files
Remove double PCIe bridge mapping
The bridge was incorrectly configured with 2 overlapping mappings (0-&FFFFFFFF and another 0-&8000000). When the VL805 wanted to bus master into main memory the bridge was confused where the transaction should go, causing a master abort to be logged on the secondary side. Reorganise the PCI memory so that only a small window in the top 1GB is actively decoded (we can't bus master above 3GB anyway due to a chip design "feature"), meaning the rest of the secondary address space is forwarded 1:1 to the primary. Further, because the CPU side windows can only be sized in powers of 2, reduce that to 2GB in size.
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