Commit 872fc542 authored by ROOL's avatar ROOL 🤖
Browse files

This commit was manufactured by cvs2git to create tag 'Pi3APlus_bp'.

Sprout from master 2018-03-21 20:59:45 UTC Robert Sprowson <rsprowson@gitlab.riscosopen.org> 'Safe GPIO pins table updates'
Delete:
    Makefile
    MkClean,fd7
    MkRom,fd7
    ReadMe
    VersionNum
    hdr/CastleMacros
    hdr/DMA
    hdr/StaticWS
    hdr/UART
    s/CLib
    s/CMOS
    s/DMA
    s/Debug
    s/IIC
    s/Interrupts
    s/KbdScan
    s/Messaging
    s/RTC
    s/SPI
    s/Timers
    s/Top
    s/Touch
    s/UART
    s/USB
    s/VCHIQ
    s/Video
parent b0ddf21a
# Copyright 2012 Castle Technology Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Makefile for BCM2835 HAL
#
COMPONENT = BCM2835 HAL
TARGET = BCM2835
OBJS = Top CLib CMOS Debug Interrupts SDIO Timers UART USB Video DMA Messaging GPIO VCHIQ IIC RTC SPI Touch KbdScan
HDRS =
CMHGFILE =
CUSTOMRES = custom
CUSTOMROM = custom
ROM_TARGET = custom
LNK_TARGET = custom
AIFDBG = aif._BCM2835
#include StdRules
#include StdTools
include CModule
CCFLAGS += -ff -APCS 3/32bit/nofp/noswst
ASFLAGS += -APCS 3/nofp/noswst
AASMFLAGS += -APCS 3/nofp/noswst
resources:
@${ECHO} ${COMPONENT}: no resources
rom: aof.${TARGET}
@${ECHO} ${COMPONENT}: rom module built
_debug: ${GPADBG}
@echo ${COMPONENT}: debug image built
install_rom: linked.${TARGET}
${CP} linked.${TARGET} ${INSTDIR}.${TARGET} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
aof.${TARGET}: ${ROM_OBJS_} ${ROM_LIBS} ${DIRS} ${ROM_DEPEND}
${LD} -o $@ -aof ${ROM_OBJS_} ${ROM_LIBS}
linked.${TARGET}: aof.${TARGET}
${LD} ${LDFLAGS} ${LDLINKFLAGS} -o $@ -bin -base 0xFC000000 aof.${TARGET}
${AIFDBG}: ${ROM_OBJS_} ${ROM_LIBS}
${MKDIR} aif
${LD} -aif -bin -d -o ${AIFDBG} ${ROM_OBJS_} ${ROM_LIBS}
#${GPADBG}: ${AIFDBG}
# ToGPA -s ${AIFDBG} ${GPADBG}
# Dynamic dependencies:
Dir <Obey$Dir>
amu_machine clean
stripdepnd
Dir <Obey$Dir>
amu_machine rom _debug linked.BCM2835 THROWBACK=-throwback
Note that this component is currently under the "mixed" hierarchy because it
contains a mixture of BSD and shared-source licenced code - but the vast
majority is BSD. If you are doing any work on this HAL, please ask before
creating or importing any shared-source code here. There is a possibility
that this HAL may be used by NetBSD, and we need to keep the code BSD
licenced for it to be of use to them.
Ben, 2012-05-13
/* (0.75)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.75
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 21 Mar 2018
#define Module_MajorVersion "0.75"
#define Module_Version 75
#define Module_MinorVersion ""
#define Module_Date "21 Mar 2018"
#define Module_ApplicationDate "21-Mar-18"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.75"
#define Module_HelpVersion "0.75 (21 Mar 2018)"
#define Module_LibraryVersionInfo "0:75"
; Copyright 2012 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
MACRO
HALEntry $name
ASSERT (. - HAL_EntryTable) / 4 = EntryNo_$name
DCD $name - HAL_EntryTable
MEND
MACRO
NullEntry
DCD HAL_Null - HAL_EntryTable
MEND
MACRO
CallOSM $entry, $reg
LDR ip, [v8, #$entry*4]
MOV lr, pc
ADD pc, v8, ip
MEND
MACRO
CallOS $entry, $tailcall
ASSERT $entry <= HighestOSEntry
[ "$tailcall"=""
MOV lr, pc
|
[ "$tailcall"<>"tailcall"
! 0, "Unrecognised parameter to CallOS"
]
]
LDR pc, OSentries + 4*$entry
MEND
END
;
; Copyright (c) 2012, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; General registers, from DMA_Base
DMA_INT_STATUS * &fe0
DMA_ENABLE * &ff0
; DMA control block
^ 0
DMACB_TI # 4
DMACB_SOURCE_AD # 4
DMACB_DEST_AD # 4
DMACB_TXFR_LEN # 4
DMACB_STRIDE # 4
DMACB_NEXTCONBK # 4
DMACB_RESERVED # 8
DMACB_SIZE * @
DMACB_ALIGN * 32
; DMA channel register map
^ 0
DMACH_CS # 4 ; RW
DMACH_CONBLK_AD # 4 ; RW
DMACH_TI # 4 ; RO
DMACH_SOURCE_AD # 4 ; RO
DMACH_DEST_AD # 4 ; RO
DMACH_TXFR_LEN # 4 ; RO
DMACH_STRIDE # 4 ; RO
DMACH_NEXTCONBK # 4 ; RO (RW when paused)
DMACH_DEBUG # 4 ; RW
; Stride of 256 bytes between each channel
DMA_CH_STRIDE * &100
; Register/CB bits
DMA_CS_RESET * 1<<31
DMA_CS_ABORT * 1<<30
DMA_CS_DISDEBUG * 1<<29
DMA_CS_WAIT_FOR_OUTSTANDING_WRITES * 1<<28
DMA_CS_PANIC_PRIORITY_SHIFT * 20
DMA_CS_PANIC_PRIORITY_MASK * &F
DMA_CS_PRIORITY_SHIFT * 16
DMA_CS_PRIORITY_MASK * &F
DMA_CS_ERROR * 1<<8
DMA_CS_WAITING_FOR_OUTSTANDING_WRITES * 1<<6
DMA_CS_DREQ_STOPS_DMA * 1<<5
DMA_CS_PAUSED * 1<<4
DMA_CS_DREQ * 1<<3
DMA_CS_INT * 1<<2
DMA_CS_END * 1<<1
DMA_CS_ACTIVE * 1<<0
DMA_TI_NO_WIDE_BURSTS * 1<<26
DMA_TI_WAITS_SHIFT * 21
DMA_TI_WAITS_MASK * &F
DMA_TI_PERMAP_SHIFT * 16
DMA_TI_PERMAP_MASK * &1F
DMA_TI_BURST_LENGTH_SHIFT * 12
DMA_TI_BURST_LENGTH_MASK * &F
DMA_TI_SRC_IGNORE * 1<<11
DMA_TI_SRC_DREQ * 1<<10
DMA_TI_SRC_WIDTH * 1<<9
DMA_TI_SRC_INC * 1<<8
DMA_TI_DEST_IGNORE * 1<<7
DMA_TI_DEST_DREQ * 1<<6
DMA_TI_DEST_WIDTH * 1<<5
DMA_TI_DEST_INC * 1<<4
DMA_TI_WAIT_RESP * 1<<3
DMA_TI_TDMODE * 1<<1 ; Not in lite channels
DMA_TI_INTEN * 1<<0
DMA_TXFR_LEN_YLENGTH_SHIFT * 16 ; Not in lite channels
DMA_TXFR_LEN_YLENGTH_MASK * &3FFF
DMA_TXFR_LEN_XLENGTH_SHIFT * 0
DMA_TXFR_LEN_XLENGTH_MASK * &FFFF
DMA_TXFR_LEN_D_STRIDE_SHIFT * 16
DMA_TXFR_LEN_D_STRIDE_MASK * &FFFF
DMA_TXFR_LEN_S_STRIDE_SHIFT * 16
DMA_TXFR_LEN_S_STRIDE_MASK * &FFFF
DMA_DEBUG_LITE * 1<<28
DMA_DEBUG_VERSION_SHIFT * 25
DMA_DEBUG_VERSION_MASK * &7
DMA_DEBUG_DMA_STATE_SHIFT * 16
DMA_DEBUG_DMA_STATE_MASK * &FF
DMA_DEBUG_DMA_ID_SHIFT * 8
DMA_DEBUG_DMA_ID_MASK * &FF
DMA_DEBUG_OUTSTANDING_WRITES_SHIFT * 4
DMA_DEBUG_OUTSTANDING_WRITES_MASK * &F
DMA_DEBUG_READ_ERROR * 1<<2
DMA_DEBUG_FIFO_ERROR * 1<<1
DMA_DEBUG_READ_LAST_NOT_SET_ERROR * 1<<0
; Peripheral DREQ values
DREQ_NONE * 0
DREQ_DSI1 * 1
DREQ_PCM_TX * 2
DREQ_PCM_RX * 3
DREQ_SMI * 4
DREQ_PWM * 5
DREQ_SPI_TX * 6
DREQ_SPI_RX * 7
DREQ_BSC_SPI_SLAVE_TX * 8
DREQ_BSC_SPI_SLAVE_RX * 9
DREQ_EMMC * 11
DREQ_UART_TX * 12
DREQ_SD_HOST * 13
DREQ_UART_RX * 14
DREQ_DSI2 * 15
DREQ_SLIMBUS_MC_TX * 16
DREQ_HDMI * 17
DREQ_SLIMBUS_MC_RX * 18
DREQ_SLIMBUS_DC0 * 19
DREQ_SLIMBUS_DC1 * 20
DREQ_SLIMBUS_DC2 * 21
DREQ_SLIMBUS_DC3 * 22
DREQ_SLIMBUS_DC4 * 23
DREQ_SCALER_FIFO_0_SMI * 24
DREQ_SCALER_FIFO_1_SMI * 25
DREQ_SCALER_FIFO_2_SMI * 26
DREQ_SLIMBUS_DC5 * 27
DREQ_SLIMBUS_DC6 * 28
DREQ_SLIMBUS_DC7 * 29
DREQ_SLIMBUS_DC8 * 30
DREQ_SLIMBUS_DC9 * 31
; Channels 7-14 are lite channels
DMA_CH_is_lite * &7F80
END
;
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; With many thanks to Broadcom Europe Ltd for releasing the source code to
; its Linux drivers, thus making this port possible.
;
GET Hdr:OSEntries
GET Hdr:HALDevice
GET Hdr:SDHCIDevice
GET Hdr:DMADevice
GET Hdr:GPIODevice
GET Hdr:VideoDevice
GET hdr.BCM2835
; Per-timer workspace layout
^ 0
Timer_Reload # 4 ; interval between interrupts
Timer_Compare # 4 ; soft copy of most recently programmed compare value
Timer_Register # 4 ; address of compare register
Timer_Device # 4 ; device number
TimerWsSize * :INDEX: @
; Per-DMA channel workspace
^ 0, a1
DMACDevice # HALDevice_DMAL_Size
DMACWorkspace # 4 ; HAL workspace ptr
DMACChanMask # 4 ; DMA_ENABLE bit for this channel
DMACDREQ # 4 ; Peripheral/DREQ this channel is servicing
DMACOptions # 4 ; Options set by SetOptions
DMACPeriAddress # 4 ; VC phys addr of peripheral - i.e. at &7e......
DMACLastProgress # 4 ; Last progress value
DMACLastCONBLK_AD # 4 ; Last control block seen executing
DMACLastTXFR_LEN # 4 ; Last transfer length remaining seen
DMACCBOffset # 4 ; Address offset to convert DMA CB addr to ARM CB addr
DMACDesc # 32 ; Buffer for description string
DMAC_DeviceSize * :INDEX: @
; VCHIQ HAL device layout
^ 0
# HALDeviceSize
HALDevice_VCHIQARMToVCOffset # 4
HALDevice_VCHIQVCDoorbell # 4 ; Doorbell to interrupt VC
HALDevice_VCHIQARMDoorbell # 4 ; Doorbell to interrupt us
HALDevice_VCHIQInitVC # 4
HALDevice_VCHIQ_Size * :INDEX: @
; Device-specific struct for the VDU device
^ 0
VDUDevSpec_SizeField # 4 ; Size field
VDUDevSpec_DMAChan # 4 ; Pointer to DMA channel
VDUDevSpec_BurstLen # 4 ; Burst length for use with DMA channel
VDUDevSpec_Size # 0 ; Size value to write to size field
; Main workspace layout
sb RN 9
^ 0,sb
PeriBase # 4
IRQ_Base_Address # 4
ARM_Counter_IO_Address # 4
ARM_Timer_IO_Address # 4
UARTOldModemStatus # 4
MMUOffBaseAddr # 4 ; original address kernel was loaded from
MachineID # 8 ; derived from MAC address if there
IIC_Status # 4 ; Non-zero if an IIC transfer is going on
; NOTE - The following locations are for the base addresses of the
; controllers that RISC OS uses for bus 0 and bus 1. The use is
; dependent on board revision. Revision 1 boards (Board_Revision
; values 0..3) use Broadcom controller 0 for RISC OS bus 0 and
; Broadcom 1 for RISC OS 1. Revision 2 boards (Board_Revision
; values 4 upwards) use Broadcom controller 1 for RISC OS bus 0
; and Broadcom controller 0 for RISC OS bus 1, because the PCB
; layout exchanged the busses.
IIC_Base # 4 ; Base address of IIC controller for RO bus 0
; # 4 ; Base address of IIC controller for RO bus 1
; NOTE - Bus 1 isn't yet implemented!
Timer SETA 0
WHILE Timer < NumTimers
Timer$Timer.Ws # TimerWsSize
Timer SETA Timer + 1
WEND
FB_CacheMode # 4
; info interrogated from the VC side
ARM_Base # 4
ARM_Size # 4
VC_Base # 4
VC_Size # 4
Board_Model # 4
Board_Revision # 4
ARM_DMAChannels # 4
VirtGPIOBuf # 4
SafetyCatch # 4 ; Only valid on Compute Module 3
; align to 16 byte boundary NB this isnt aligned once hal initialised
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
tagbuffer # 300 ; platform query buffer
NCNBAddr # 4 ;NCNB workspace
NCNBPhysAddr # 4 ;VC physical address of NCNB workspace
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
SimulatedCMOS # 2048+4 ;Usual 2k plus version word (as appended by *SaveCMOS)
SDHCIWriteInterval # 4 ; minimum counter ticks between writes
SDHCILastWriteCount # 4 ; counter value at last write
SDHCIInputClock # 4 ; estimated speed of input clock to SDHCI block
# (16-:INDEX:@):AND:15 ; align nicely
SDHCIDevice # HALDevice_SDHCISize ; see Hdr:SDHCIDevice
SDHCISlotInfo # HALDeviceSDHCI_SlotInfo_Size ; the controller has just the 1 slot
DMAFreeChannels # 4 ; Mask of which physical DMA channels are free
DMANumChannels # 4 ; Count of how many channel devices exist
DMAChannelList # DMA_CH_Count*4 ; List of channel devices for Enumerate
# (16-:INDEX:@):AND:15 ; align nicely
DMAController # HALDevice_DMAC_Size_0_1 ; see Hdr:HALDevice
DMAChannels # DMAC_DeviceSize*DMA_CH_Count ; List of channel devices (indexed by physical channel #)
VCHIQDevice # HALDevice_VCHIQ_Size
GPIO0Device # HALDevice_GPIO_Size_1_0 + 16
GPIO1Device # HALDevice_GPIO_Size_1_0 + 16
VDUDevice # HALDevice_VDU_Size
VDUDevSpec # VDUDevSpec_Size
RTCDeviceStruct # 80
SPI0Device # HALDeviceSize
SPI1Device # HALDeviceSize
SPI2Device # HALDeviceSize
TouchDevice # HALDeviceSize
MBoxDevice # HALDeviceSize
HAL_WsSize * :INDEX:@
sizeof_workspace * :INDEX:@
END
;
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; With many thanks to Broadcom Europe Ltd for releasing the source code to
; its Linux drivers, thus making this port possible.
;
; UART clock
UARTCLK * 3000000
; UARTCR bits
CR_CTSEN * 1:SHL:16 ; Hardware CTS
CR_RTSEN * 1:SHL:15 ; Hardware RTS
CR_RTS * 1:SHL:11 ; RTS
CR_RXE * 1:SHL:9 ; RX enable
CR_TXE * 1:SHL:8 ; TX enable
CR_LBE * 1:SHL:7 ; Loopback
CR_UARTEN * 1:SHL:0 ; UART enable
; UARTLCRH bits
LCRH_SPS * 1:SHL:7 ; Sticky parity
LCRH_WLEN * 3:SHL:5 ; Word length
LCRH_WLEN_shift * 5
LCRH_FEN * 1:SHL:4 ; FIFO enable
LCRH_STP2 * 1:SHL:3 ; 2 stop bits
LCRH_EPS * 1:SHL:2 ; Even parity
LCRH_PEN * 1:SHL:1 ; Parity enable
LCRH_BRK * 1:SHL:0 ; Break enable
; UARTFLAG bit assignments
FLAG_TXFE * 7 ; TX FIFO empty
FLAG_RXFF * 6 ; RX FIFO full
FLAG_TXFF * 5 ; TX FIFO full
FLAG_RXFE * 4 ; RX FIFO empty
FLAG_BUSY * 3 ; UART busy transmitting
FLAG_CTS * 0
; UARTDR bit assignments
DR_OE * 11 ; Overrun error
DR_BE * 10 ; Break error
DR_PE * 9 ; Parity error
DR_FE * 8 ; Framing error
; UARTRSRECR bit assignments
RSR_OE * 3 ; Overrun error
RSR_BE * 2 ; Break error
RSR_PE * 1 ; Parity error
RSR_FE * 0 ; Framing error
; UARTIMSC, UARTRIS, UARTMIS, UARTICR bit assignments
UI_OE * 10 ; Overrun error
UI_BE * 9 ; Break error
UI_PE * 8 ; Parity error
UI_FE * 7 ; Framing error
UI_RT * 6 ; RX timeout
UI_TX * 5 ; TX FIFO empty threshold crossed
UI_RX * 4 ; RX FIFO full threshold crossed
UI_CTS * 1 ; CTS
END
;
; Copyright (c) 2012, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
EXPORT memcpy
AREA |Asm$$Code|, CODE, READONLY, PIC
; A really simple implementation, just so it has a consistent licence
; In:
; a1 = dest
; a2 = source
; a3 = size in bytes (assumed a multiple of 4)
; Out:
; a1 preserved
memcpy ROUT
MOV a4, a1
B %F10
01 LDR ip, [a2], #4
STR ip, [a4], #4
10 SUBS a3, a3, #4
BCS %B01
MOV pc, lr
END
;
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.