Commit 2579b887 authored by Ben Avison's avatar Ben Avison
Browse files

Complete rework of timer and interrupt code

Detail:
 * Moved interrupt and timer code out of s.Stubs - they're not stubs any more.
 * Rewrote timer and counter code to use GPU system timer 1 for our Timer0
   rather than the ARM timer. This is recommended in the Broadcom datasheet
   because it's driven from the APB clock and so its speed will vary in
   reduced or low power mode.
 * HAL_CounterDelay now, well, does a delay!
 * Added a Timer1, driven from GPU system timer 3 - common code with Timer0.
 * Reshuffled device numbers so the GPU interrupts are at the bottom. This
   works better for FIQs and makes Timer0 the lowest priority interrupt.
 * Higher device numbers are now consistently treated as higher priority.
 * Stopped using bits 8-31 of the basic interrupt registers. These can't be
   masked, so they cause the kernel to lock up if generated, which happens
   if the GPU interrupt which they alias is generated (which appears to
   include the timers even though this is not documented).
 * Added definitions for all the interrupts, including those redacted from the
   datasheet - we need them at least for timers, USB and SD.
 * Stopped HAL_IRQClear from doing anything - this interrupt controller
   doesn't do latching. To acknowledge timer interrupts, you should use
   HAL_TimerIRQClear (and HAL_IRQClear too for compatibility with other ports).
 * Implemented HAL_IRQStatus and all the FIQ control routines.
 * Offsets to interrupt controller registers now use symbolic names.
 * Replaced some hard spaces in sources with normal ones.
Admin:
  Tested on a beta Raspberry Pi. Confirmed that interrupt handlers for both
  ARM and GPU sources can both be operational simultaneuosly. However, the FIQ
  code has not been tested. Timer0 is verified as running at the correct
  speed and reporting a count *down* in the correct range (not a count up as
  some previous versions did). HAL_CounterDelay appears correct also.

Version 0.04. Tagged as 'BCM2835-0_04'
parent bfd45048
......@@ -17,7 +17,7 @@
COMPONENT = BCM2835 HAL
TARGET = BCM2835
OBJS = Top CMOS Debug Display Stubs UART USB Video
OBJS = Top CMOS Debug Display Interrupts Stubs Timers UART USB Video
HDRS =
CMHGFILE =
......
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.03"
Module_Version SETA 3
Module_MajorVersion SETS "0.04"
Module_Version SETA 4
Module_MinorVersion SETS ""
Module_Date SETS "23 May 2012"
Module_ApplicationDate SETS "23-May-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.03"
Module_HelpVersion SETS "0.03 (23 May 2012)"
Module_FullVersion SETS "0.04"
Module_HelpVersion SETS "0.04 (23 May 2012)"
END
/* (0.03)
/* (0.04)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.03
#define Module_MajorVersion_CMHG 0.04
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 23 May 2012
#define Module_MajorVersion "0.03"
#define Module_Version 3
#define Module_MajorVersion "0.04"
#define Module_Version 4
#define Module_MinorVersion ""
#define Module_Date "23 May 2012"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.03"
#define Module_HelpVersion "0.03 (23 May 2012)"
#define Module_LibraryVersionInfo "0:3"
#define Module_FullVersion "0.04"
#define Module_HelpVersion "0.04 (23 May 2012)"
#define Module_LibraryVersionInfo "0:4"
;
;Copyright(c)2012, RISC OS Open Ltd
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
;Allrightsreserved.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
......@@ -182,6 +182,27 @@ $label MCR$cond p6, 0, $r, c6, c1
$label WriteWDTCR $r,$cond
$label MCR$cond p6, 0, $r, c7, c1
MEND
GBLA NumTimers
NumTimers SETA 0
MACRO
DeclareTimer $phys
TimerPhysFromLog$NumTimers * $phys
NumTimers SETA NumTimers + 1
MEND
; List of physical timers (excluding those already used by VideoCore)
; in the order we use them for logical timers
DeclareTimer 1
DeclareTimer 3
; An assembly-time variable for looping over all logical timers, since
; the available timers might vary with version of start.elf
GBLA Timer
;
; Mailbox 0
;
......@@ -242,23 +263,39 @@ MB_Pwr_CCP2TX_MASK * 8
MACRO
$label DataSyncBarrier $r, $cond
$label MOV$cond $r, #0
[ {UAL}
MCR$cond p15, #0, $r, c7, c10, #4
|
MCR$cond p15, 0, $r, c7, c10,4
]
MEND
MACRO
$label DoMemBarrier $r, $cond
$label MOV$cond $r, #0
[ {UAL}
MCR$cond p15, #0, $r, c7, c10, #5
|
MCR$cond p15, 0, $r, c7, c10,5
]
MEND
MACRO
$label FlushDataCache $r, $cond
$label MOV$cond $r, #0
[ {UAL}
MCR$cond p15, #0, $r, c7, c6, #0
|
MCR$cond p15, 0, $r, c7, c6,0
]
MEND
MACRO
$label FlushDataCacheRange $startaddr,$endaddr,$cond
$label BIC$cond $startaddr, $startaddr, #&1f
BIC$cond $endaddr, $endaddr, #&1f
[ {UAL}
MCRR$cond p15, #0, $endaddr, $startaddr, c14
|
MCRR$cond p15, 0, $endaddr, $startaddr, c14
]
MEND
; GPIO register set
GPIO_Base * &00200000 ; base offset of GPIO regs
......@@ -338,8 +375,17 @@ UARTITIP * &84 ; integr test ip
UARTITOP * &88 ; integ test op
UARTTDR * &8c ; test data reg
; Timer
; GPU System Timer
Timer_Base * &00003000 ; base of system timer regs
ST_CS * &00 ; control/status
ST_CLO * &04 ; counter low
ST_CHI * &08 ; counter high
ST_C0 * &0C ; compare 0
ST_C1 * &10 ; compare 1
ST_C2 * &14 ; compare 2
ST_C3 * &18 ; compare 3
; ARM Timer
ARM_Timer_Base * &0000b400 ; base of ARM timer regs
; DMA registers
......@@ -370,50 +416,117 @@ ISP_Base * &00a00000 ; ISP
; Interrupt handling
;
IRQ_Base * &0000B200
; Raspberry Pi interrupt sources.. there are several, with
; odd placing. all convcentrated int 3 32bit registers.
; The bottom 5 bits are the bit within the register, the next 2 the register
; there are a total of 21 interrupts in the main IRQ register
; and 64 possible ones in the GPU registers
; Not all are identified...
; so..
iDev_ARM_Timer * 0
iDev_ARM_Mbx * 1
iDev_ARM_DBell0 * 2
iDev_ARM_DBell1 * 3
iDev_ARM_GPU0Hlt * 4
iDev_ARM_GPU1Hlt * 5
iDev_ARM_IllegAcs1 * 6
iDev_ARM_IllegAcs0 * 7
iDev_IRQ_Pend1 * 8
iDev_IRQ_Pend2 * 9
iDev_GPU_IRQ7 * 10
iDev_GPU_IRQ9 * 11
iDev_GPU_IRQ10 * 12
iDev_GPU_IRQ18 * 13
iDev_GPU_IRQ19 * 14
iDev_GPU_IRQ53 * 15
iDev_GPU_IRQ54 * 16
iDev_GPU_IRQ55 * 17
iDev_GPU_IRQ56 * 18
iDev_GPU_IRQ57 * 19
iDev_GPU_IRQ62 * 20
; devices in register 1 - start at 32
iDev_GPU_AuxInt * 32+29
; devices in register 2 - start at 64
iDev_GPU_i2cslv * 32+43
iDev_GPU_pwa0 * 32+45
iDev_GPU_pwa1 * 32+46
iDev_GPU_smi * 32+48
iDev_GPU_ioi0 * 32+49
iDev_GPU_ioi1 * 32+50
iDev_GPU_ioi2 * 32+51
iDev_GPU_ioi3 * 32+52
iDev_GPU_i2c * 32+53
iDev_GPU_spi * 32+54
iDev_GPU_pcm * 32+55
iDev_GPU_Uart * 32+57
IRQ_PENDB * &00 ; read: pending basic interrupts (devices 64-95)
IRQ_PEND1 * &04 ; read: pending interrupts 1 (GPU IRQs 0-31, devices 0-31)
IRQ_PEND2 * &08 ; read: pending interrupts 2 (GPU IRQs 32-63, devices 32-63)
IRQ_FIQCTL * &0C ; FIQ control register
IRQ_EN1 * &10 ; read: enabled interrupts 1; write: bits to OR into enabled interrupts 1
IRQ_EN2 * &14 ; read: enabled interrupts 2; write: bits to OR into enabled interrupts 2
IRQ_ENB * &18 ; read: enabled basic interrupts; write: bits to OR into enabled basic interrupts
IRQ_DIS1 * &1C ; read: enabled interrupts 1; write: bits to BIC from enabled interrupts 1
IRQ_DIS2 * &20 ; read: enabled interrupts 2; write: bits to BIC from enabled interrupts 2
IRQ_DISB * &24 ; read: enabled basic interrupts; write: bits to BIC from enabled basic interrupts
; Raspberry Pi interrupt sources.
; Because the pending and enable registers are listed in different orders, there are 2 logical ways to map these onto
; device numbers. However, matching the order of the enable registers has the following advantages:
; * the same device numbers can be used in the FIQ control register without modification
; * the GPU timer interrupts end up with the lowest priority - desirable since we run our counter from them
; devices in register 1 - start at 0
iDev_GPU_Timer0 * 0 ; not on list in datasheet
iDev_GPU_Timer1 * 1 ; not on list in datasheet
iDev_GPU_Timer2 * 2 ; not on list in datasheet
iDev_GPU_Timer3 * 3 ; not on list in datasheet
iDev_GPU_Codec0 * 4 ; not on list in datasheet
iDev_GPU_Codec1 * 5 ; not on list in datasheet
iDev_GPU_Codec2 * 6 ; not on list in datasheet
iDev_GPU_VCJPEG * 7 ; not on list in datasheet
iDev_GPU_ISP * 8 ; not on list in datasheet
iDev_GPU_VCUSB * 9 ; not on list in datasheet
iDev_GPU_VC3D * 10 ; not on list in datasheet
iDev_GPU_Transp * 11 ; not on list in datasheet
iDev_GPU_MCSync0 * 12 ; not on list in datasheet
iDev_GPU_MCSync1 * 13 ; not on list in datasheet
iDev_GPU_MCSync2 * 14 ; not on list in datasheet
iDev_GPU_MCSync3 * 15 ; not on list in datasheet
iDev_GPU_DMA0 * 16 ; not on list in datasheet
iDev_GPU_DMA1 * 17 ; not on list in datasheet
iDev_GPU_VCDMA2 * 18 ; not on list in datasheet
iDev_GPU_VCDMA3 * 19 ; not on list in datasheet
iDev_GPU_DMA4 * 20 ; not on list in datasheet
iDev_GPU_DMA5 * 21 ; not on list in datasheet
iDev_GPU_DMA6 * 22 ; not on list in datasheet
iDev_GPU_DMA7 * 23 ; not on list in datasheet
iDev_GPU_DMA8 * 24 ; not on list in datasheet
iDev_GPU_DMA9 * 25 ; not on list in datasheet
iDev_GPU_DMA10 * 26 ; not on list in datasheet
iDev_GPU_DMA11 * 27 ; not on list in datasheet
iDev_GPU_DMA12 * 28 ; not on list in datasheet
iDev_GPU_AuxInt * 29
iDev_GPU_ARM * 30 ; not on list in datasheet
iDev_GPU_VPUDMA * 31 ; not on list in datasheet
; devices in register 2 - start at 32
iDev_GPU_HostPort * 32 ; not on list in datasheet
iDev_GPU_VidScale * 33 ; not on list in datasheet
iDev_GPU_CCP2TX * 34 ; not on list in datasheet
iDev_GPU_SDC * 35 ; not on list in datasheet
iDev_GPU_DSI0 * 36 ; not on list in datasheet
iDev_GPU_AVE * 37 ; not on list in datasheet
iDev_GPU_Cam0 * 38 ; not on list in datasheet
iDev_GPU_Cam1 * 39 ; not on list in datasheet
iDev_GPU_HDMI0 * 40 ; not on list in datasheet
iDev_GPU_HDMI1 * 41 ; not on list in datasheet
iDev_GPU_PixVal1 * 42 ; not on list in datasheet
iDev_GPU_I2CSPISlv * 43
iDev_GPU_DSI1 * 44 ; not on list in datasheet
iDev_GPU_PWA0 * 45
iDev_GPU_PWA1 * 46
iDev_GPU_CPR * 47 ; not on list in datasheet
iDev_GPU_SMI * 48
iDev_GPU_GPIO0 * 49
iDev_GPU_GPIO1 * 50
iDev_GPU_GPIO2 * 51
iDev_GPU_GPIO3 * 52
iDev_GPU_I2C * 53
iDev_GPU_SPI * 54
iDev_GPU_PCM * 55
iDev_GPU_SDIO * 56 ; not on list in datasheet
iDev_GPU_Uart * 57
iDev_GPU_SlimBus * 58 ; not on list in datasheet
iDev_GPU_Vec * 59 ; not on list in datasheet
iDev_GPU_CPG * 60 ; not on list in datasheet
iDev_GPU_RNG * 61 ; not on list in datasheet
iDev_GPU_VCSDIO * 62 ; not on list in datasheet
iDev_GPU_AVSPMON * 63 ; not on list in datasheet
iDev_ARM_Timer * 64+0
iDev_ARM_Mbx * 64+1
iDev_ARM_DBell0 * 64+2
iDev_ARM_DBell1 * 64+3
iDev_ARM_GPU0Hlt * 64+4
iDev_ARM_GPU1Hlt * 64+5
iDev_ARM_IllegAcs1 * 64+6
iDev_ARM_IllegAcs0 * 64+7
; Notice that bits 8-31 of the pending basic interrupts cannot be masked. This causes the RISC OS kernel problems,
; because the default action for an unhandled interrupt is to mask it, and if masking doesn't work, we end up with an
; infinite loop. You *could* map these device numbers back to bits in the disable interrupts 1/2 registers, but it's
; not a simple mapping and the same bits appear in the pending interrupts 1/2 registers as well, so they're arguably
; not much use. Is the saving of one or two reads of the pending interrupt registers worth the complexity? I don't know.
; It's also worth noting that these device numbers are not valid for use as FIQs. So for now, I recommend you don't use
; these devices - use the equivalents in the GPU interrupt registers instead.
iDev_ARM_MiscGPU1 * 64+8 ; OR of GPU IRQs 0-31 excluding those listed below
iDev_ARM_MiscGPU2 * 64+9 ; OR of GPU IRQs 32-63 excluding those listed below
iDev_ARM_VCJPEG * 64+10 ; copy of GPU IRQ 7
iDev_ARM_VCUSB * 64+11 ; copy of GPU IRQ 9
iDev_ARM_VC3D * 64+12 ; copy of GPU IRQ 10
iDev_ARM_VCDMA2 * 64+13 ; copy of GPU IRQ 18
iDev_ARM_VCDMA3 * 64+14 ; copy of GPU IRQ 19
iDev_ARM_I2C * 64+15 ; copy of GPU IRQ 53
iDev_ARM_SPI * 64+16 ; copy of GPU IRQ 54
iDev_ARM_PCM * 64+17 ; copy of GPU IRQ 55
iDev_ARM_SDIO * 64+18 ; copy of GPU IRQ 56
iDev_ARM_Uart * 64+19 ; copy of GPU IRQ 57
iDev_ARM_VCSDIO * 64+20 ; copy of GPU IRQ 62
MACRO
$label ReadINTCTL $r,$cond
......
;
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
; All rights reserved.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
......@@ -33,6 +33,16 @@
GET Hdr:OSEntries
GET hdr.BCM2835
; Per-timer workspace layout
^ 0
Timer_Reload # 4 ; interval between interrupts
Timer_Compare # 4 ; soft copy of most recently programmed compare value
Timer_Register # 4 ; address of compare register
Timer_Device # 4 ; device number
TimerWsSize * :INDEX: @
; Main workspace layout
sb RN 9
......@@ -46,6 +56,12 @@ UARTFCRSoftCopy # 4
DMAcb # sizeof_DMAcb
Timer SETA 0
WHILE Timer < NumTimers
Timer$Timer.Ws # TimerWsSize
Timer SETA Timer + 1
WEND
FB_Base # 4
FB_Size # 4
FB_CacheMode # 4
......
;
; Copyright (c) 2012, RISC OS Open Ltd
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of RISC OS Open Ltd nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
EXPORT Interrupt_Init
EXPORT HAL_IRQEnable
EXPORT HAL_IRQDisable
EXPORT HAL_IRQClear
EXPORT HAL_IRQSource
EXPORT HAL_IRQStatus
EXPORT HAL_FIQEnable
EXPORT HAL_FIQDisable
EXPORT HAL_FIQDisableAll
EXPORT HAL_FIQClear
EXPORT HAL_FIQSource
EXPORT HAL_FIQStatus
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET hdr.BCM2835
GET hdr.StaticWS
AREA |ARM$$code|, CODE, READONLY, PIC
; One-time initialisation
Interrupt_Init
LDR a1, PeriBase
ADD a1, a1, #IRQ_Base
STR a1, IRQ_Base_Address
MOV pc, lr
HAL_IRQEnable
CMN a1,#1
MOVEQ pc,lr
LDR ip, IRQ_Base_Address
ADD ip, ip, #IRQ_EN1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
LDR a4, [ip, a3, LSL #2] ; get old enable mask
STR a2, [ip, a3, LSL #2] ; enable our bit
AND a1, a2, a4 ; test our bit in old mask
MOV pc, lr
HAL_IRQDisable
CMN a1,#1
MOVEQ pc,lr
LDR ip, IRQ_Base_Address
ADD ip, ip, #IRQ_DIS1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
LDR a4, [ip, a3, LSL #2] ; get old enable mask
STR a2, [ip, a3, LSL #2] ; disable our bit
AND a1, a2, a4 ; test our bit in old mask
MOV pc, lr
HAL_IRQClear
HAL_FIQClear
; There is no latching of interrupts in this interrupt controller,
; so nothing to clear
MOV pc, lr
HAL_IRQSource
LDR a2, IRQ_Base_Address
LDRB a1, [a2, #IRQ_PENDB] ; note, LDRB so we ignore bits 8-31
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_ARM_Timer ; 64
MOVPL pc, lr
LDR a1, [a2, #IRQ_PEND2]
CLZ a1, a1
RSBS a1, a1, #31
ADDPL a1, a1, #iDev_GPU_HostPort ; 32
MOVPL pc, lr
LDR a1, [a2, #IRQ_PEND1]
CLZ a1, a1
RSB a1, a1, #31
MOV pc, lr
HAL_IRQStatus
HAL_FIQStatus
; This interrupt controller does not allow us to see the status of the interrupt request
; lines prior to masking by the interrupt enable register, which is the defined result
; of this call. The closest we can do is checking whether the stated device is interrupting.
CMN a1,#1
MOVEQ pc,lr
LDR ip, IRQ_Base_Address
ASSERT IRQ_PENDB = 0
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
SUBS a3, a3, #2 ; rotate register because pending regs are in a different order
ADDMI a3, a3, #3
LDR a4, [ip, a3, LSL #2] ; get pending mask
AND a1, a2, a4 ; test our bit
MOV pc, lr
FIQEnable * 1<<7
FIQSourceMask * &7F
HAL_FIQEnable
CMN a1,#1
MOVEQ pc,lr
LDR ip, IRQ_Base_Address
LDRB a3, [ip, #IRQ_FIQCTL] ; LDRB helpfully masks out bits 8-31 for us
ORR a4, a1, #FIQEnable
TEQ a3, a4 ; Z set => FIQs already enabled
STR a4, [ip, #IRQ_FIQCTL]
ADD ip, ip, #IRQ_EN1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; enable our bit
MOVEQ a1, #1
MOVNE a1, #0
MOV pc, lr
HAL_FIQDisable
CMN a1,#1
MOVEQ pc,lr
LDR ip, IRQ_Base_Address
ADD ip, ip, #IRQ_DIS1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; disable our bit
LDRB a3, [ip, #IRQ_FIQCTL-IRQ_DIS1] ; LDRB helpfully masks out bits 8-31 for us
ORR a4, a1, #FIQEnable
TEQ a3, a4 ; Z set => FIQs already enabled
MOV a4, #0
STR a4, [ip, #IRQ_FIQCTL-IRQ_DIS1]
MOVEQ a1, #1
MOVNE a1, #0
MOV pc, lr
HAL_FIQDisableAll
LDR ip, IRQ_Base_Address
LDR a1, [ip, #IRQ_FIQCTL]
TST a1, #FIQEnable
MOVEQ pc, lr ; FIQs weren't enabled
AND a1, a1, #FIQSourceMask
ADD ip, ip, #IRQ_DIS1
MOV a2, #1
AND a3, a1, #&1F ; get bit in register
MOV a2, a2, LSL a3 ; bitmask
MOV a3, a1, LSR #5 ; shift to get relevant register
STR a2, [ip, a3, LSL #2] ; disable our bit
MOV pc, lr
HAL_FIQSource
; There can only be one, the configured FIQ device
LDR ip, IRQ_Base_Address
LDR a1, [ip, #IRQ_FIQCTL]
AND a1, a1, #FIQSourceMask
MOV pc, lr
END
;
;Copyright(c)2012, RISC OS Open Ltd
; Copyright (c) 2012, RISC OS Open Ltd
; Copyright (c) 2012, Adrian Lees
;Allrightsreserved.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
......@@ -45,33 +45,6 @@
IMPORT output_text
IMPORT output_text_at
]
EXPORT Interrupt_Init
EXPORT HAL_IRQEnable
EXPORT HAL_IRQDisable
EXPORT HAL_IRQClear
EXPORT HAL_IRQSource
EXPORT HAL_IRQStatus
EXPORT HAL_FIQEnable
EXPORT HAL_FIQDisable
EXPORT HAL_FIQDisableAll
EXPORT HAL_FIQClear
EXPORT HAL_FIQSource
EXPORT HAL_FIQStatus
EXPORT Timer_Init
EXPORT HAL_Timers
EXPORT HAL_TimerDevice
EXPORT HAL_TimerGranularity
EXPORT HAL_TimerMaxPeriod
EXPORT HAL_TimerSetPeriod
EXPORT HAL_TimerPeriod
EXPORT HAL_TimerReadCountdown
EXPORT HAL_TimerIRQClear
EXPORT HAL_CounterRate
EXPORT HAL_CounterPeriod
EXPORT HAL_CounterRead
EXPORT HAL_CounterDelay
EXPORT HAL_IICBuses
EXPORT HAL_IICType
......@@ -110,213 +83,6 @@
]
MEND
; interrupt pending registers are
; basic & 0ffset 0, pending 1 @ +4 and pending 2 @ +8
; set amd clear are pending 1 @ +0 and pending 2 @ +4 and basic @ +8
; device numbering is optimised for handling irqs
Interrupt_Init
LDR R0,PeriBase
ADD R0,R0,#IRQ_Base
STR R0,IRQ_Base_Address
MOV pc, lr
HAL_IRQEnable
CMN a1,#1
MOVEQ pc,lr
LDR R12,IRQ_Base_Address
ADD R12,R12,#&10 ; IRQ_Enables1
MOV R1,#1
MOV R3,R0,LSR #5 ; shift to get relevant register
SUBS R3,R3,#1
MOVMI r3,#2 ; reorder which register
AND R2,R0,#&1F ; get bit in register
MOV R1,R1,LSL R2