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;
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; Copyright (c) 2012, RISC OS Open Ltd
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; Copyright (c) 2012, Adrian Lees
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; All rights reserved.
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;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in the
;       documentation and/or other materials provided with the distribution.
;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
;       may be used to endorse or promote products derived from this software
;       without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; With many thanks to Broadcom Europe Ltd for releasing the source code to
; its Linux drivers, thus making this port possible.
;

        AREA    |!!!ROMStart|, CODE, READONLY, PIC

        GET     Hdr:ListOpts
        GET     Hdr:Macros
        GET     Hdr:System
        GET     Hdr:Machine.<Machine>
        GET     Hdr:HALSize.<HALSize>
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        GET     Hdr:MEMM.VMSAv6
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        GET     Hdr:FSNumbers
        GET     Hdr:NewErrors
        GET     Hdr:BCMSupport
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        GET     Hdr:HALEntries

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        GET     hdr.BCM2835
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        GET     hdr.StaticWS
        GET     hdr.CastleMacros

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        IMPORT  Interrupt_Init
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        IMPORT  InterruptVC6_Init
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        IMPORT  ARM11_HAL_IRQEnable
        IMPORT  ARM11_HAL_IRQDisable
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        IMPORT  ARM11_HAL_IRQClear
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        IMPORT  ARM11_HAL_IRQSource
        IMPORT  ARM11_HAL_IRQStatus
        IMPORT  ARM11_HAL_FIQEnable
        IMPORT  ARM11_HAL_FIQDisable
        IMPORT  ARM11_HAL_FIQDisableAll
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        IMPORT  ARM11_HAL_FIQClear
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        IMPORT  ARM11_HAL_FIQSource
        IMPORT  ARM11_HAL_FIQStatus
        IMPORT  ARM11_HAL_IRQMax
        IMPORT  ARM11_HAL_IRQProperties
        IMPORT  QA7_HAL_IRQEnable
        IMPORT  QA7_HAL_IRQDisable
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        IMPORT  QA7_HAL_IRQClear
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        IMPORT  QA7_HAL_IRQSource
        IMPORT  QA7_HAL_IRQStatus
        IMPORT  QA7_HAL_FIQEnable
        IMPORT  QA7_HAL_FIQDisable
        IMPORT  QA7_HAL_FIQDisableAll
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        IMPORT  QA7_HAL_FIQClear
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        IMPORT  QA7_HAL_FIQSource
        IMPORT  QA7_HAL_FIQStatus
        IMPORT  QA7_HAL_IRQMax
        IMPORT  QA7_HAL_IRQProperties
        IMPORT  QA7_HAL_IRQSetCores
        IMPORT  QA7_HAL_IRQGetCores
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        IMPORT  VC6_HAL_IRQEnable
        IMPORT  VC6_HAL_IRQDisable
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        IMPORT  VC6_HAL_IRQClear
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        IMPORT  VC6_HAL_IRQSource
        IMPORT  VC6_HAL_IRQStatus
        IMPORT  VC6_HAL_FIQEnable
        IMPORT  VC6_HAL_FIQDisable
        IMPORT  VC6_HAL_FIQDisableAll
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        IMPORT  VC6_HAL_FIQClear
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        IMPORT  VC6_HAL_FIQSource
        IMPORT  VC6_HAL_FIQStatus
        IMPORT  VC6_HAL_IRQMax
        IMPORT  VC6_HAL_IRQProperties
        IMPORT  VC6_HAL_IRQSetCores
        IMPORT  VC6_HAL_IRQGetCores
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        IMPORT  Timer_Init
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        IMPORT  HAL_Timers
        IMPORT  HAL_TimerDevice
        IMPORT  HAL_TimerGranularity
        IMPORT  HAL_TimerMaxPeriod
        IMPORT  HAL_TimerSetPeriod
        IMPORT  HAL_TimerPeriod
        IMPORT  HAL_TimerReadCountdown
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        IMPORT  HAL_TimerIRQClear
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        IMPORT  HAL_CounterRate
        IMPORT  HAL_CounterPeriod
        IMPORT  HAL_CounterRead
        IMPORT  HAL_CounterDelay

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        IMPORT  IIC_Init
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        IMPORT  HAL_IICBuses
        IMPORT  HAL_IICType
        IMPORT  HAL_IICTransfer
        IMPORT  HAL_IICMonitorTransfer

        IMPORT  HAL_NVMemoryType
        IMPORT  HAL_NVMemorySize
        IMPORT  HAL_NVMemoryPageSize
        IMPORT  HAL_NVMemoryProtectedSize
        IMPORT  HAL_NVMemoryProtection
        IMPORT  HAL_NVMemoryRead
        IMPORT  HAL_NVMemoryWrite

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        IMPORT  PCI_Init
        IMPORT  HAL_PCIReadConfigByte
        IMPORT  HAL_PCIReadConfigHalfword
        IMPORT  HAL_PCIReadConfigWord
        IMPORT  HAL_PCIWriteConfigByte
        IMPORT  HAL_PCIWriteConfigHalfword
        IMPORT  HAL_PCIWriteConfigWord
        IMPORT  HAL_PCISlotTable
        IMPORT  HAL_PCIAddresses

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        IMPORT  HAL_UARTPorts
        IMPORT  HAL_UARTStartUp
        IMPORT  HAL_UARTShutdown
        IMPORT  HAL_UARTFeatures
        IMPORT  HAL_UARTReceiveByte
        IMPORT  HAL_UARTTransmitByte
        IMPORT  HAL_UARTLineStatus
        IMPORT  HAL_UARTInterruptEnable
        IMPORT  HAL_UARTRate
        IMPORT  HAL_UARTFormat
        IMPORT  HAL_UARTFIFOSize
        IMPORT  HAL_UARTFIFOClear
        IMPORT  HAL_UARTFIFOEnable
        IMPORT  HAL_UARTFIFOThreshold
        IMPORT  HAL_UARTInterruptID
        IMPORT  HAL_UARTBreak
        IMPORT  HAL_UARTModemControl
        IMPORT  HAL_UARTModemStatus
        IMPORT  HAL_UARTDevice
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        IMPORT  HAL_UARTDefault
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 [ Debug
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        IMPORT  HAL_DebugRX
        IMPORT  HAL_DebugTX
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 ]
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        IMPORT  HAL_PlatformName
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        IMPORT  HAL_KbdScanDependencies
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        IMPORT  HAL_USBControllerInfo
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        IMPORT  SDIO_InitDevices

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        IMPORT  DMA_InitDevices

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        IMPORT  GPIO_InitDevices

        IMPORT  VCHIQ_InitDevices

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        IMPORT  Video_InitDevices

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        IMPORT  RTC_InitDevices

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        IMPORT  SPI_InitDevices

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        IMPORT  EtherNIC_InitDevices

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        IMPORT  Touch_InitDevices

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        IMPORT  BCMMBox_InitDevices

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        IMPORT  DBell_InitDevices

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        IMPORT  HAL_SendHostMessage
        IMPORT  HAL_QueryPlatform
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        IMPORT  GetVCBuffer
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        EXPORT  HAL_Base
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        IMPORT  memcpy
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     [ HALDebug
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        EXPORT  HAL_DebugHexTX4
        EXPORT  HAL_DebugTXStrInline
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     ]

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        EXPORT  reset
        EXPORT  workspace
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        ENTRY
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HAL_Base

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reset   B       start
undef   B       undefined_instr
swi     B       swi_instr
pabort  B       prefetch_abort
dabort  B       data_abort
irq     B       interrupt
fiq     B       fast_interrupt
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        ; exception handlers just for use during HAL init,
        ;   in case something goes wrong
undefined_instr
        B       .
swi_instr
        B       .
prefetch_abort
        B       .
data_abort
        B       .
interrupt
        B       .
fast_interrupt
        B       .

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        ALIGN   256
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atags   ; list of 'atags' structures constructed here by the loader code
        ; running on VideoCore, describing
        ; - available memory
        ; - command line parameters, including framebuffer parameters
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        ALIGN   4096
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end_stack
workspace
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        %       sizeof_workspace
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        ALIGN   32768
        ASSERT  . - HAL_Base = 32768
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start
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        CPUDetect lr
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        BCC     %F02                     ; no MPIDR or HYP mode in ARM1176

        ; Sometimes a secondary CPU gets here (indicates a bug somewhere)
        ; Prevent it doing any further damage if so
        MRC     p15, 0, lr, c0, c0, 5   ; read MPIDR
        TST     lr, #&FF
01      WFINE
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        BNE     %BT01
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        ; Some versions of the firmware call us in HYP mode, which requires
        ; a secret handshake to drop into SVC mode
        MRS     lr, CPSR
        AND     lr, lr, #M32_bits
        TEQ     lr, #HYP32_mode
        BNE     %F02

        ADR     lr, %F03
        MSR     SPSR_cxsf, #F32_bit+I32_bit+SVC32_mode
        MSR     SPSR_x, #A32_bit
        MSR     elr_hyp, lr
        ERET
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        MSR     CPSR_c,#F32_bit+I32_bit+SVC32_mode
03
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        ADRL    v1, HAL_Base + OSROM_HALSize    ; v1 -> RISC OS image
        LDR     v8, [v1, #OSHdr_Entries]
        ADD     v8, v8, v1                      ; v8 -> RISC OS entry table
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        ; Ensure CPU is 'set up' (typically enables ICache)
        MOV     a1, #0
        CallOSM OS_InitARM
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        ADRL    sb,workspace
        ADRL    R13,end_stack
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        ADRL    r4, reset
        STR     r4, MMUOffBaseAddr
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        CPUDetect r4
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        LDRCC   r4,=IO_Base_BCM2835
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        LDREQ   r4,=IO_Base_BCM2836
        LDRHI   r4,=IO_Base_BCM2838
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        STR     r4,PeriBase
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        LDRHI   r4,=IO_Base2_BCM2838
        STRHI   r4,PeriBase2
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        ; Query the platform
        BL      HAL_QueryPlatform

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 [ HALDebug
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        mov     a1, #0
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        bl      HAL_UARTStartUp          ; start early for debug use
        bl      HAL_DebugTXStrInline
        DCB     "HalStartup",10,0
        ALIGN
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   [ {FALSE} ; Dump out the boot stub for debugging
        MOV     v1, #0
        MOV     v2, #256
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        MOV     a1, v1
        bl      HAL_DebugHexTX4
        LDR     a1, [v1], #4
        BL      HAL_DebugHexTX4
        MOV     a1, #10
        BL      HAL_DebugTX
        CMP     v1, v2
        BNE     %BT10
   ]
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 ]
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 [ JTAG
        ; Configure the GPIO pins used for JTAG
        LDR     a1, PeriBase
        ADD     a1, a1, #GPIO_Base
        LDR     a2, [a1, #GPFSel2]
        LDR     a3, =&3f00003f
        AND     a2, a2, a3 ; Keep settings for 20, 21, 28, 29
        LDR     a3, =(3<<6)+(3<<9)+(3<<12)+(3<<15)+(3<<18)+(3<<21) ; Set 22-27 to alt4
        ORR     a2, a2, a3
        STR     a2, [a1, #GPFSel2]
 ]

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        ; Enable USB power
        ; Note - may need changing to enable other devices in future
        ; Looks like we need to write the logical OR of all the devices we want enabled
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        MOV     r1, #0
        LDR     r0,=(16:SHL:MB_Pwr_USB)+MB_Chan_Pwr
        BL      HAL_SendHostMessage

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        ; From config.txt we might have loaded some CMOS settings above the ROM,
        ; import those into our workspace (they may subsequently turn out to be junk)
        ADRL    a1, HAL_Base + OSROM_HALSize
        LDR     a3, [a1, #OSHdr_ImageSize]
        ADD     a2, a3, a1              ; loaded immediately after OS image
        ADR     a1, SimulatedCMOS
        LDR     a3, =?SimulatedCMOS
        BL      memcpy

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 [ HALDebug
        bl      HAL_DebugTXStrInline
        DCB     "HalStartup2",10,0
        ALIGN
 ]
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        LDR     v3, ARM_Base
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        LDR     v7, ARM_End2
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      [ HALDebug
        ADRL    a1, reset
        BL      HAL_DebugHexTX4
        MOV     a1, v3
        BL      HAL_DebugHexTX4
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        MOV     a1, v7
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        BL      HAL_DebugHexTX4
        BL      HAL_DebugTXStrInline
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        DCB     "ROM start, RAM start, RAM end", 10, 0
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        ALIGN
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      ]
relocate_code
        ; Relocate ROM to high end of RAM
        ADRL    v1, HAL_Base + OSROM_HALSize
        LDR     v2, [v1, #OSHdr_ImageSize]
        LDR     lr, [v1, #OSHdr_Flags]
        TST     lr, #OSHdrFlag_SupportsCompression
        LDRNE   lr, [v1, #OSHdr_CompressedSize]
        MOVEQ   lr, v2
        SUB     v1, v1, #OSROM_HALSize ; Start of HAL
        ADD     v2, v2, #OSROM_HALSize ; Size of HAL+OS
        ADD     lr, lr, #OSROM_HALSize ; Size of compressed HAL+OS
        ADD     v5, v1, lr ; End of OS
        SUB     ip, v7, v2 ; New start address of HAL
        CMP     v1, ip
        BEQ     relocate_10 ; No copy needed
        CMP     v1, v7
        BHI     relocate_20 ; We're in some ROM above RAM. OK to continue with copy.
        CMP     v5, ip
        BLS     relocate_20 ; We're in some ROM/RAM below our copy destination. OK to continue with copy.
        ; Else we currently overlap the area we want to copy ourselves into.
        SUB     ip, v1, lr ; Copy the HAL+OS to just before itself.
relocate_20
        MOV     a1, ip ; Copy dest
        MOV     a2, v1 ; Copy source
        MOV     a3, lr ; Copy length
relocate_30
        LDR     a4, [a2], #4
        SUBS    a3, a3, #4
        STR     a4, [a1], #4
        BGT     relocate_30
        MOV     a1, #0
        MCR     p15, 0, a1, c7, c10, 4 ; drain write buffer
        MCR     p15, 0, a1, c7, c5, 0 ; invalidate I-Cache
        ; Jump to our new copy
        ADR     a1, relocate_code
        SUB     a2, ip, v1
        ADD     a1, a1, a2 ; relocate our branch target
        ADD     v8, v8, a2 ; Update OS entry table ptr
        MOV     pc, a1
relocate_10
        ; Copy completed, reset stack & workspace ptrs
        ADD     sp, v3, #4096 ; Use RAM for stack instead of bits of ROM
        ADRL    sb, workspace ; However workspace is still in ROM :(
      [ HALDebug
        BL      HAL_DebugTXStrInline
        DCB     "ROM relocated", 10, 0
        ALIGN
      ]

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        ; If we're a multi-core chip, the other cores should be sat in a boot
        ; stub located at &0, waiting for us to give them the address of some
        ; code to execute. Move them into a holding space in the relocated ROM
        ; so that we don't break them when we overwrite the boot stub.
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        CPUDetect lr
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        BCC     clear_ram
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        LDREQ   a1, =INT_BASE_BCM2836
        LDRHI   a1, =INT_BASE_BCM2838
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        MVN     a2, #0
        STR     a2, [a1, #QA7_CORE0_MBOX1_RDCLR] ; Clear our mailboxes
        STR     a2, [a1, #QA7_CORE0_MBOX2_RDCLR]
        STR     a2, [a1, #QA7_CORE0_MBOX3_RDCLR]
        DSB
        ADR     a2, holding_pattern
        STR     a2, [a1, #QA7_CORE1_MBOX3_SET] ; Each core is sat waiting for mailbox 3
        STR     a2, [a1, #QA7_CORE2_MBOX3_SET]
        STR     a2, [a1, #QA7_CORE3_MBOX3_SET]
        DSB
        SEV     ; Current boot stub just has the cores in a spin loop, but use SEV just in case future stubs are more power-conscious
        ; Now wait for the cores to acknowledge the request (input via our mailboxes)
        MOV     a3, #1<<20 ; Timeout
        MOV     a4, #QA7_CORE0_MBOX1_RDCLR
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        SUBS    a3, a3, #1
        BEQ     %FT20
        LDR     a2, [a1, a4]
        CMP     a2, #0
        BEQ     %BT10
        CMP     a4, #QA7_CORE0_MBOX3_RDCLR
        ADDNE   a4, a4, #QA7_CORE0_MBOX2_RDCLR-QA7_CORE0_MBOX1_RDCLR
        BNE     %BT10
      [ HALDebug
        BL      HAL_DebugTXStrInline
        DCB     "Aux cores in holding pattern", 10, 0
        ALIGN
        B       %FT25
      ]
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      [ HALDebug
        BL       HAL_DebugTXStrInline
        DCB      "Failed waking cores", 10, 0
        ALIGN
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      ]

clear_ram
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        ; Clear RAM
        ; v3 is start of RAM
        ; ip is end of RAM/start of ROM
        ; Note this code will clear the stack, but there shouldn't be anything on it yet anyway
        MOV     a1, ip
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        LDR     v2, ARM_Base2
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        MOV     a2, #0
        MOV     a3, #0
        MOV     a4, #0
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        MOV     v1, #0
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        MOV     v4, #0
        MOV     v5, #0
        MOV     v7, #0
        MOV     lr, #0
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clear_lp1
        STMDB   a1!,{a2-a4,v1,v4,v5,v7,lr}
        STMDB   a1!,{a2-a4,v1,v4,v5,v7,lr}
        STMDB   a1!,{a2-a4,v1,v4,v5,v7,lr}
        STMDB   a1!,{a2-a4,v1,v4,v5,v7,lr}
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        TEQ     a1, v2
        LDREQ   a1, ARM_End
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        CMP     a1, v3
        BHI     clear_lp1
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        MOV     a1, #0  ; AddRAM reference handle (NULL for first call)
        Push    "a1, ip"
        LDR     a2, ARM_Base
        LDR     a3, ARM_End
        CMP     a3, ip
        MOVHI   a3, ip
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 [ HALDebug
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        BL      HAL_DebugTXStrInline
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        DCB     "HalStartup3 .. rst  rend",10,0
        ALIGN
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        MOV     a1, a2
        BL      HAL_DebugHexTX4
        MOV     a1, a3
        BL      HAL_DebugHexTX4
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        MOV     a1, #0
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 ]
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        MVN     a4, #0
        CallOSM OS_AddRAM
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        STR     a1, [sp] ; ref for next call
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        MOV     a1, #0
        LDR     a2, ARM_Base2
        LDR     a3, [sp, #4]
        CMP     a3, a2
        BLS     %FT01 ; no second block of RAM
 [ HALDebug
        BL      HAL_DebugTXStrInline
        DCB     "HalStartup4 .. rst  rend",10,0
        ALIGN
        MOV     a1, a2
        BL      HAL_DebugHexTX4
        MOV     a1, a3
        BL      HAL_DebugHexTX4
        MOV     a1, #0
 ]
        MVN     a4, #0
        CallOSM OS_AddRAM
        STR     a1, [sp] ; ref for next call
01
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        ; OS kernel informed of RAM areas
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        LDR     a2, PeriBase
        ADD     a2, a2, #PM_Base
        LDR     a2, [a2, #PM_RSTS] ; consider reset status
        TST     a2, #PM_RSTS_HADPOR

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        Pull    "a4,ip"      ; a4 = ref from last AddRAM
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        MOV     a1, #OSStartFlag_RAMCleared
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        ORRNE   a1, a1, #OSStartFlag_POR
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        ADRL    a2, HAL_Base + OSROM_HALSize       ; a2 -> RISC OS image
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        CPUDetect a3
        ADRCCL  a3, HALdescriptor
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        ADREQL  a3, QA7_HALdescriptor
        ADRHIL  a3, VC6_HALdescriptor
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        CallOSM OS_Start

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        ; OS_Start doesn't return....invokes HAL_Init after MMU activation
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holding_pattern
        ; Auxilliary cores arrive here
        ; First, work out who we are
        MRC     p15, 0, a1, c0, c0, 5 ; Read MPIDR
        AND     a1, a1, #3            ; Extract core number (should be 1-3)
      [ HALDebug
        DSB
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        CPUDetect a2
        LDREQ   a2, =IO_Base_BCM2836+UART_Base
        LDRHI   a2, =IO_Base_BCM2838+UART_Base
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        ADD     a3, a1, #'0'
        STRB    a3, [a2, #UARTDR]
      ]
        DSB
        ; Clear our mailbox register
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        CPUDetect a2
        LDREQ   a2, =INT_BASE_BCM2836
        LDRHI   a2, =INT_BASE_BCM2838
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        ADD     a3, a2, #QA7_CORE0_MBOX0_SET
        ADD     a3, a3, a1, LSL #2    ; Box to reply to core 0 on
        ADD     a4, a2, #QA7_CORE0_MBOX3_RDCLR
        ADD     a4, a4, a1, LSL #4    ; Box to receive instructions via
        MVN     v1, #0
        STR     v1, [a4]
        DSB
        ; Let the master core know that we're here
        STR     pc, [a3]              ; Any non-zero should do
        ; Now wait for further instruction
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        WFE
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        LDR     v1, [a4]
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        CMP     v1, #0
        BEQ     %BT10
      [ HALDebug
        DSB
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        CPUDetect a2
        LDREQ   a2, =IO_Base_BCM2836+UART_Base
        LDRHI   a2, =IO_Base_BCM2838+UART_Base
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        ADD     a3, a1, #'0'
        STRB    a3, [a2, #UARTDR]
      ]
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        ; Ensure the GIC is enabled
        CPUDetect a1
        BLS     %FT20
        LDR     v2, =INT_BASE_BCM2838+GICC_Base
        MOV     a1, #&FF
        STR     a1, [v2, #GICC_PMR] ; Highest PMR value = any priority interrupt will pass the test
        MOV     a1, #3
        STR     a1, [v2, #GICC_BPR] ; gggg.ssss binary point? not used ATM
        ; Enable CPU interface
        MOV     a1, #&61
        STR     a1, [v2, #GICC_CTLR]
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        ADR     lr, holding_pattern   ; Allow return to the holding pattern to simplify testing
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        BX      v1

        LTORG

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; Generate three HAL descriptors - one for ARM11 based systems, one for A7/A53
; and one for A72.
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; This allows us to avoid extra overheads in some critical routines
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; Entries created using 'VarEntry' will use either ARM11_$name, QA7_$name or VC6_$name
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        GBLA    table_idx
        GBLA    entries
        GBLS    descriptor
        GBLS    table

table_idx SETA 0

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        WHILE   table_idx < 3
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 [ table_idx == 0
descriptor SETS "HALdescriptor"
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 ELIF table_idx == 1
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descriptor SETS "QA7_HALdescriptor"
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 |
descriptor SETS "VC6_HALdescriptor"
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 ]
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table SETS "$descriptor._EntryTable"

$table DATA
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        HALEntry HAL_Init

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        VarEntry HAL_IRQEnable
        VarEntry HAL_IRQDisable
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        VarEntry HAL_IRQClear
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        VarEntry HAL_IRQSource
        VarEntry HAL_IRQStatus
        VarEntry HAL_FIQEnable
        VarEntry HAL_FIQDisable
        VarEntry HAL_FIQDisableAll
638
        VarEntry HAL_FIQClear
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        VarEntry HAL_FIQSource
        VarEntry HAL_FIQStatus
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        HALEntry HAL_Timers
        HALEntry HAL_TimerDevice
        HALEntry HAL_TimerGranularity
        HALEntry HAL_TimerMaxPeriod
        HALEntry HAL_TimerSetPeriod
        HALEntry HAL_TimerPeriod
        HALEntry HAL_TimerReadCountdown

        HALEntry HAL_CounterRate
        HALEntry HAL_CounterPeriod
        HALEntry HAL_CounterRead
        HALEntry HAL_CounterDelay

        HALEntry HAL_NVMemoryType
        HALEntry HAL_NVMemorySize
        HALEntry HAL_NVMemoryPageSize
        HALEntry HAL_NVMemoryProtectedSize
        HALEntry HAL_NVMemoryProtection
        NullEntry ; HAL_NVMemoryIICAddress
        HALEntry HAL_NVMemoryRead
        HALEntry HAL_NVMemoryWrite

        HALEntry HAL_IICBuses
        HALEntry HAL_IICType
        NullEntry ; HAL_IICSetLines
        NullEntry ; HAL_IICReadLines
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        NullEntry ; HAL_IICDevice
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        HALEntry HAL_IICTransfer
        HALEntry HAL_IICMonitorTransfer

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        NullEntry ; HAL_VideoFlybackDevice
        NullEntry ; HAL_VideoSetMode
        NullEntry ; HAL_VideoWritePaletteEntry
        NullEntry ; HAL_VideoWritePaletteEntries
        NullEntry ; HAL_VideoReadPaletteEntry
        NullEntry ; HAL_VideoSetInterlace
        NullEntry ; HAL_VideoSetBlank
        NullEntry ; HAL_VideoSetPowerSave
        NullEntry ; HAL_VideoUpdatePointer
        NullEntry ; HAL_VideoSetDAG
        NullEntry ; HAL_VideoVetMode
        NullEntry ; HAL_VideoPixelFormats
        NullEntry ; HAL_VideoFeatures
        NullEntry ; HAL_VideoBufferAlignment
        NullEntry ; HAL_VideoOutputFormat
687

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        VarEntry HAL_IRQProperties
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      [ table_idx == 0
        NullEntry
        NullEntry
        NullEntry
        NullEntry
        NullEntry
      |
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        VarEntry HAL_IRQSetCores
        VarEntry HAL_IRQGetCores
        VarEntry HAL_CPUCount
        VarEntry HAL_CPUNumber
        VarEntry HAL_SMPStartup
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      ]
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        HALEntry HAL_MachineID

        HALEntry HAL_ControllerAddress
        HALEntry HAL_HardwareInfo
        HALEntry HAL_SuperIOInfo
        HALEntry HAL_PlatformInfo
        NullEntry ; HALEntry HAL_CleanerSpace

        HALEntry HAL_UARTPorts
        HALEntry HAL_UARTStartUp
        HALEntry HAL_UARTShutdown
        HALEntry HAL_UARTFeatures
        HALEntry HAL_UARTReceiveByte
        HALEntry HAL_UARTTransmitByte
        HALEntry HAL_UARTLineStatus
        HALEntry HAL_UARTInterruptEnable
        HALEntry HAL_UARTRate
        HALEntry HAL_UARTFormat
        HALEntry HAL_UARTFIFOSize
        HALEntry HAL_UARTFIFOClear
        HALEntry HAL_UARTFIFOEnable
        HALEntry HAL_UARTFIFOThreshold
        HALEntry HAL_UARTInterruptID
        HALEntry HAL_UARTBreak
        HALEntry HAL_UARTModemControl
        HALEntry HAL_UARTModemStatus
        HALEntry HAL_UARTDevice
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        HALEntry HAL_UARTDefault
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      [ Debug
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        HALEntry HAL_DebugRX
        HALEntry HAL_DebugTX
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      |
        NullEntry ; HAL_DebugRX
        NullEntry ; HAL_DebugTX
      ]
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        NullEntry ; HAL_PCIFeatures
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      [ table_idx == 2
        HALEntry HAL_PCIReadConfigByte
        HALEntry HAL_PCIReadConfigHalfword
        HALEntry HAL_PCIReadConfigWord
        HALEntry HAL_PCIWriteConfigByte
        HALEntry HAL_PCIWriteConfigHalfword
        HALEntry HAL_PCIWriteConfigWord
        NullEntry ; HAL_PCISpecialCycle
        HALEntry HAL_PCISlotTable
        HALEntry HAL_PCIAddresses
      |
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        NullEntry ; HAL_PCIReadConfigByte
        NullEntry ; HAL_PCIReadConfigHalfword
        NullEntry ; HAL_PCIReadConfigWord
        NullEntry ; HAL_PCIWriteConfigByte
        NullEntry ; HAL_PCIWriteConfigHalfword
        NullEntry ; HAL_PCIWriteConfigWord
        NullEntry ; HAL_PCISpecialCycle
        NullEntry ; HAL_PCISlotTable
        NullEntry ; HAL_PCIAddresses
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      ]
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        HALEntry HAL_PlatformName
        NullEntry
        NullEntry
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        HALEntry HAL_InitDevices

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        HALEntry HAL_KbdScanDependencies
        NullEntry
        NullEntry
        NullEntry
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        HALEntry HAL_PhysInfo

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        HALEntry HAL_Reset
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        VarEntry HAL_IRQMax
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        HALEntry HAL_USBControllerInfo
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        NullEntry ; HAL_USBPortPower
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        NullEntry ; HAL_USBPortIRQStatus
        NullEntry ; HAL_USBPortIRQClear
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        NullEntry ; HAL_USBPortDevice
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        HALEntry  HAL_TimerIRQClear
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        NullEntry ; HAL_TimerIRQStatus

        HALEntry HAL_ExtMachineID

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entries SETA    (.-$table)/4

$descriptor     DATA
        DCD     HALFlag_NCNBWorkspace
        DCD     HAL_Base - $descriptor
        DCD     OSROM_HALSize
        DCD     $table - $descriptor
        DCD     &$entries
        DCD     sizeof_workspace

table_idx SETA table_idx+1
        WEND
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;--------------------------------------------------------------------------------------
; HAL Initialisation callback from OS kernel
;--------------------------------------------------------------------------------------

HAL_Init
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        Push    "v5, lr"
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        MOV     v5, a2
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        BL      SetUpOSEntries
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        CPUDetect a2
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        LDRCC   a2, =IO_Base_BCM2835
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        BCC     %FT05

        ; Map in the A7/A53 control logic
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        MOV     a1, #L1_S
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        LDREQ   a2, =INT_BASE_BCM2836
        LDRHI   a2, =INT_BASE_BCM2838
        LDR     a3, =INT_SIZE
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        CallOS  OS_MapInIO
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        STR     a1, IntBase
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        CPUDetect a2
        LDREQ   a2, =IO_Base_BCM2836
        LDRHI   a2, =IO_Base_BCM2838
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        ; Map in the main IO region
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        MOVCC   a1, #0
        MOVCS   a1, #L1_S
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        LDRLS   a3, =IO_Size_BCM2835
        LDRHI   a3, =IO_Size_BCM2838
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        CallOS  OS_MapInIO
        STR     a1, PeriBase

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        ; Map in the secondary IO region
        CPUDetect a2
        BLS     %FT06
        MOV     a1, #L1_S
        LDR     a2, =IO_Base2_BCM2838
        LDR     a3, =IO_Size2_BCM2838
        CallOS  OS_MapInIO
        STR     a1, PeriBase2
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        ; Recover various values that are now trapped in ROM from when the workspace
        ; and ROM overlapped prior to relocation. Copy them into RW memory at sb.
        ADRL    a4, workspace           ; where they are post ROM relocation

        LDR     a1, [a4, #:INDEX:FB_CacheMode]
        STR     a1, FB_CacheMode        ; GPU cache mode

        LDR     a3, [a4, #:INDEX:VC_Size]
        LDR     a2, [a4, #:INDEX:VC_Base]
        LDR     a1, [a4, #:INDEX:ARM_Base]
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        LDR     ip, [a4, #:INDEX:ARM_End]
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        STR     a3, VC_Size
        STR     a2, VC_Base
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        STR     a1, ARM_Base
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        STR     ip, ARM_End
        LDR     a1, [a4, #:INDEX:ARM_Base2]
        LDR     ip, [a4, #:INDEX:ARM_End2]
        STR     a1, ARM_Base2
        STR     ip, ARM_End2
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        LDR     a3, [a4, #:INDEX:Board_Model]
        LDR     a2, [a4, #:INDEX:Board_Revision]
        LDR     a1, [a4, #:INDEX:ARM_DMAChannels]
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        LDR     ip, [a4, #:INDEX:SafetyCatch]
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        STR     a3, Board_Model
        STR     a2, Board_Revision
        STR     a1, ARM_DMAChannels
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        STR     ip, SafetyCatch
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        ; Model is expected to be 0, to save checking it elsewhere halt
        ; if it looks wrong
        MOVS    a3, a3
        BNE     .

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        LDR     a3, [a4, #:INDEX:EMMCClock]
        LDR     a2, [a4, #:INDEX:CoreClock]
        STR     a3, EMMCClock
        STR     a2, CoreClock

 [ Debug
        MOV     a1,#0                   ; start the uart ..we use it for debug
        BL      HAL_UARTStartUp         ; restart to capture logical io address
   [ HALDebug
        bl      HAL_DebugTXStrInline
        DCB     "HalStart from OS",10,0
        ALIGN
   ]
 ]
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     [ HALDebug
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        LDR     a1, VC_Base
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        BL      HAL_DebugHexTX4
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        LDR     a1, VC_Size
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        BL      HAL_DebugHexTX4
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        BL      HAL_DebugTXStrInline
        DCB     "VC memory",10,0
        ALIGN
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     ]
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        ; Get the physical address of NCNB workspace
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        ; v5 -> start of NCNB workspace
        STR     v5, NCNBAddr
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        MOV     a1, v5
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        CallOS  OS_LogToPhys
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        LDR     a3, FB_CacheMode
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        ORR     a1, a1, a3
        STR     a1, NCNBPhysAddr
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        ; Try and initialise virtual GPIO buffer
        LDR     a1, =ARM2VC_Tag_GetVirtGPIOBuf
        MOV     a2, #4096               ; should only need a word, but request a whole page for safety (avoid getting caught out if they make the buffer bigger in future)
        LDR     a3, =ARM2VC_Tag_SetVirtGPIOBuf
        BL      GetVCBuffer
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        STR     a1, VirtGPIOBuf
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        BL      CMOS_Init
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        ; initialise our interrupts
        CPUDetect a1
        ADR     lr, %FT50
        BHI     InterruptVC6_Init
        B       Interrupt_Init
50
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        BL      Timer_Init
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        BL      IIC_Init
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        BL      PCI_Init
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     [ HALDebug
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        BL      HAL_DebugTXStrInline
        DCB     "HAL Init completed",10,0
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        ALIGN
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     ]

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        Pull    "v5, pc"
940

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; Initialise the simulated CMOS.
CMOS_Init ROUT
        Push    "v1, lr"
        ADRL    a1, workspace           ; where it got relocated to
        ADD     v1, a1, #:INDEX:SimulatedCMOS
        LDR     a4, [v1, #?SimulatedCMOS - 4]
        SUB     a4, a4, #500            ; Check version word is from RISC OS 5
        CMP     a4, #100
        BHS     %FT10

        ; Now we need to take the logical CMOS file order and make it physical
        ; The resulting layout from logical is [F0-FF][C0-EF][00-BF][100-END]
        ADR     a1, SimulatedCMOS
        ADD     a2, v1, #&F0
        MOV     a3, #16*1
        BL      memcpy
        ADD     a1, a1, #16*1
        ADD     a2, v1, #&C0
        MOV     a3, #16*3
        BL      memcpy
        ADD     a1, a1, #16*3
        ADD     a2, v1, #0
        MOV     a3, #16*12
        BL      memcpy
        ADD     a1, a1, #16*12
        ADD     a2, v1, #&100
        MOV     a3, #?SimulatedCMOS - 4 - &100
        BL      memcpy
        Pull    "v1, pc"
10
        ADR     a1, SimulatedCMOS
        MOV     a2, #-1                 ; Zap it to a known blank state
        LDR     a3, =?SimulatedCMOS - 4
20
        STR     a2, [a1, a3]
        SUBS    a3, a3, #4
        BPL     %BT20
        Pull    "v1, pc"

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; Initialise and relocate the entry table.
SetUpOSEntries  ROUT
        STR     a1, OSheader
        LDR     a2, [a1, #OSHdr_NumEntries]
        CMP     a2, #HighestOSEntry+1
        MOVHI   a2, #HighestOSEntry+1

        ADRL    a3, OSentries
        LDR     a4, [a1, #OSHdr_Entries]
        ADD     a4, a4, a1

05      SUBS    a2, a2, #1
        LDR     ip, [a4, a2, LSL #2]
        ADD     ip, ip, a4
        STR     ip, [a3, a2, LSL #2]
        BNE     %BT05

        MOV     pc, lr

HAL_ControllerAddress
        MOV     a1, #0
        MOV     pc, lr

HAL_HardwareInfo
        LDR     ip, =&FFFFFF00
        STR     ip, [a1]
        MOV     ip, #0
        STR     ip, [a2]
        LDR     ip, =&00FFFF00
        STR     ip, [a3]
        MOV     pc, lr

HAL_PlatformInfo
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        CPUDetect ip
        MOVHI   ip, #2_10010    ; no podules, PCI cards, no multi CPU, no soft off, and soft ROM
        MOVLS   ip, #2_10000    ; no podules, no PCI cards, no multi CPU, no soft off, and soft ROM
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        STR     ip, [a2]
        MOV     ip, #2_11111    ; mask of valid bits
        STR     ip, [a3]
        MOV     pc, lr

HAL_SuperIOInfo
        MOV     ip, #0
        STR     ip, [a1]
        STR     ip, [a2]
        MOV     pc, lr

HAL_MachineID
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        LDR     ip, MachAD
        LDMIA   ip, {a1, a2}
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        MOV     pc, lr
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1032
MachAD  DCD     :INDEX:workspace + :INDEX:MachineID
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HAL_ExtMachineID
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        MOV     a1, #0
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        MOV     pc, lr

HAL_Reset
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        MRS     a1, CPSR
        ORR     a1, a1, #I32_bit+F32_bit ; paranoia, don't allow reset to be interrupted
        MSR     CPSR_c, a1
1042 1043
        LDR     a1, PeriBase
        ADD     a1, a1, #PM_Base
1044
        DoMemBarrier a3
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        LDR     a2, [a1, #PM_RSTC]
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        MOV     a3, #PM_Password
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        BIC     a2, a2, #PM_RSTC_WRCFG_MASK
        ORR     a2, a2, #PM_RSTC_WRCFG_FULLRST
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        ORR     a2, a2, a3
        ADD     a3, a3, #10
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        STR     a3, [a1, #PM_WDOG]
        STR     a2, [a1, #PM_RSTC]
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        B       .
1054

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HAL_PhysInfo    ROUT
        TEQ     a1, #PhysInfo_GetTableSize
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        BNE     %FT01
        CPUDetect a2
        MOVLS   a1, #524288 ; Two pages in each byte, so (2^32)/(4096*2)
        MOVHI   a1, #4194304 ; Two pages in each byte, so (2^35)/(4096*2)
        STR     a1, [a2]
        MVN     a1, #0
        MOV     pc, lr
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        TEQ     a1, #PhysInfo_HardROM
        MOVEQ   a1, #0 ; No hard ROM
        MOVEQ   a2, #0
        STMEQIA a3, {a1-a2}
        MVNEQ   a1, #0
        MOVEQ   pc, lr

        TEQ     a1, #PhysInfo_WriteTable
        MOVNE   a1, #0
        MOVNE   pc, lr

        Push    "v1-v5,lr"
        LDR     v1, ARM_Base
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        LDR     v2, ARM_End2
        SUB     v2, v2, #1 ; make inclusive
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        STMIA   a3, {v1-v2} ; All RAM the OS knows about will be here
        ; Majority of table is unused, so prefill it
        LDR     v3, =&88888888 ; Unused regions (or RAM)
        MOV     a1, v3
        MOV     a3, v3
        MOV     a4, v3
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        CPUDetect v5
        BHI     Pi4_PhysInfo
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        ADD     v4, a2, #524288
10
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v4
        BLO     %BT10
        ; Fill in IO region
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        CPUDetect v5
1095
        SUB     a2, a2, #524288-(IO_Base_BCM2835>>13)
1096
        ADDEQ   a2, a2, #(IO_Base_BCM2836-IO_Base_BCM2835)>>13
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        ORR     a1, a1, a1, LSR #1 ; Pattern for IO regions
        ORR     a3, a3, a3, LSR #1
        ORR     a4, a4, a4, LSR #1
        ORR     v3, v3, v3, LSR #1
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        ADDLO   v5, a2, #IO_Size_BCM2835>>13
        ASSERT  IO_Base_BCM2836+IO_Size_BCM2835 = INT_BASE_BCM2836
        ADDEQ   v5, a2, #(IO_Size_BCM2835+INT_SIZE)>>13
        ASSERT  INT_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
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        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v5
        BLO     %BT20
        ; VC memory is effectively IO, so fill it in as such
        SUB     a2, v4, #524288
        LDR     v1, VC_Base
        LDR     v2, VC_Size
        ADD     a2, a2, v1, LSR #13
        ADD     v5, a2, v2, LSR #13
30
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v5
        BLO     %BT30
        MVN     a1, #0
        Pull    "v1-v5,pc"
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Pi4_PhysInfo
        ADD     v4, a2, #4194304
10
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v4
        BLO     %BT10
        ; Fill in IO region
        SUB     a2, a2, #4194304
        ADD     a2, a2, #IO_Base2_BCM2838>>13
        ORR     a1, a1, a1, LSR #1 ; Pattern for IO regions
        ORR     a3, a3, a3, LSR #1
        ORR     a4, a4, a4, LSR #1
        ORR     v3, v3, v3, LSR #1
        ADD     v5, a2, #(IO_Size2_BCM2838+IO_Size_BCM2838+INT_SIZE)>>13
        ASSERT  INT_SIZE :AND: ((2<<17)-1) = 0 ; 2 pages per table byte, 16 table bytes per iteration = 2^17 RAM bytes per iteration
20
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v5
        BLO     %BT20
        ; VC memory is effectively IO, so fill it in as such
        SUB     a2, v4, #4194304
        LDR     v1, VC_Base
        LDR     v2, VC_Size
        ADD     a2, a2, v1, LSR #13
        ADD     v5, a2, v2, LSR #13
30
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v5
        BLO     %BT30
        ; Pi 4 features a PCIe bus in the top 8 GB, fill it in as IO too
        SUB     a2, v4, #4194304-((PCIe_Base_Hi<<(32-13)) + (PCIe_Base_Lo>>13))
        ASSERT  4194304 = ((PCIe_Base_Hi + PCIe_Size_Hi)<<(32-13)) + ((PCIe_Base_Lo + PCIe_Size_Lo)>>13)
40
        STMIA   a2!, {a1,a3,a4,v3}
        CMP     a2, v4
        BLO     %BT40
        MVN     a1, #0
        Pull    "v1-v5,pc"

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HAL_Null
        MOV     pc, lr

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HAL_InitDevices
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        Push    "lr"
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        BL      Video_InitDevices ; Must be before DMA_InitDevices
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        BL      SDIO_InitDevices
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        BL      DMA_InitDevices
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        BL      GPIO_InitDevices
        BL      VCHIQ_InitDevices
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        BL      RTC_InitDevices
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        BL      SPI_InitDevices
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        BL      EtherNIC_InitDevices