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Last updated
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Fix -ve increment interactive mode *MemoryA
Debugger!5
· created
Nov 15, 2019
by
Robert Sprowson
MERGED
1
1
updated
Dec 28, 2019
Minor bugfix to alleviate the issue of ACS being mistaken for WHILE, within existing WHILE loop.
BASIC!4
· created
Dec 11, 2019
by
Kevin Swinton
MERGED
5
updated
Dec 17, 2019
Cross-compilable
DDTHdr!1
· created
Nov 04, 2019
by
Ben Avison
MERGED
0
updated
Nov 30, 2019
Add mixed-case versions of Hdr:Proc macros
HdrSrc!4
· created
Oct 09, 2019
by
Ben Avison
MERGED
2
0
updated
Nov 18, 2019
Add long descriptor page table definitions
HdrSrc!9
· created
Nov 14, 2019
by
Jeffrey Lee
MERGED
0
updated
Nov 16, 2019
Build fix
Debugger!3
· created
Oct 23, 2019
by
ROOL
MERGED
0
updated
Nov 10, 2019
Change mymrs and mymsr from Generic32 to use MRS and MSR
HdrSrc!7
· created
Oct 30, 2019
by
Timothy E Baldwin
MERGED
1
4
updated
Nov 09, 2019
Cross-compilable
ZLibMod!1
· created
Nov 04, 2019
by
Ben Avison
MERGED
0
updated
Nov 05, 2019
Add HeapReason_GetSkewAligned
HdrSrc!5
· created
Oct 24, 2019
by
Jeffrey Lee
MERGED
8
updated
Nov 02, 2019
Support large physical addresses
Debugger!2
· created
Jul 19, 2019
by
Ben Avison
MERGED
14
updated
Oct 16, 2019
Add supersection definitions to MEMM.ARM600 as well
HdrSrc!3
· created
Aug 19, 2019
by
Ben Avison
MERGED
0
updated
Aug 19, 2019
Add definitions for supersections in L1PT
HdrSrc!2
· created
Jul 13, 2019
by
Ben Avison
MERGED
3
updated
Aug 15, 2019
Add the later ARMv8 AArch32 opcodes
Debugger!1
· created
Jun 08, 2019
by
Robert Sprowson
MERGED
0
updated
Jul 06, 2019
Assemble the later ARMv8 AArch32 opcodes
BASIC!1
· created
Jun 08, 2019
by
Robert Sprowson
MERGED
0
updated
Jun 29, 2019
Add a definition of the BEN bit in SCTLR (née MMU control register)
HdrSrc!1
· created
Jun 24, 2019
by
Ben Avison
MERGED
0
updated
Jun 24, 2019
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