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Commit 30fe3ada authored by Jeffrey Lee's avatar Jeffrey Lee
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Add decgen to the misc tools 

Detail:
  Misc/decgen/* - Add a copy of decgen (http://www.phlamethrower.co.uk/riscos/decgen.php) so that it can finally start being used for generating the Debugger disassembler. This is a stripped down copy of the 1.40 release containing just the bits we need.
Admin:
  Required for building Debugger-1_85


Version 1.65. Tagged as 'Library-1_65'
parent a3f08e82
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Misc/decgen/!ReadMe 0 → 100644
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Misc/decgen/encodings/ARMv7 0 → 100644
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Misc/decgen/encodings/ARMv7_ASIMD 0 → 100644
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Misc/decgen/encodings/ARMv7_VFP 0 → 100644
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# Use:
# VFP1=(cond:4) VFP2={ne(cond,15)} for ARM
# VFP1=1110 VFP2= for Thumb2
# Note that the 'T' bit in A7.5 - A7.9 of the Thumb2 encodings has been replaced with the required value of 0 in order to cut down the number of macros needed
# Similarly, the {eq(cond,15)} ARM encodings (which require a fundamentally identical constraint for Thumb2) have also been directly replaced with the desired values (although all those lines are commented out anyway since they currently get handled by encodings in other files)
# A7.5
#11111110(opc1:4)(opc2:4)(:4)101(:1)(opc3:2)(:1)0(opc4:4) UNDEFINED # - handled by CDP2
[VFP1]1110(opc1:4)(opc2:4)(:4)101(:1)(opc3:2)(:1)0(opc4:4) [VFP2] {eq(band(opc1,11),8)} {band(opc3,1)} UNDEFINED_CDP_CDP2_A1
[VFP1]1110(opc1:4)(opc2:4)(:4)101(:1)(opc3:2)(:1)0(opc4:4) [VFP2] {eq(band(opc1,11),11)} {band(opc3,1)} {eq(opc2,6)} UNDEFINED_CDP_CDP2_A1
[VFP1]1110(opc1:4)(opc2:4)(:4)101(:1)(opc3:2)(:1)0(opc4:4) [VFP2] {eq(band(opc1,11),11)} {eq(opc3,1)} {eq(opc2,7)} UNDEFINED_CDP_CDP2_A1
[VFP1]1110(opc1:4)(opc2:4)(:4)101(:1)(opc3:2)(:1)0(opc4:4) [VFP2] {eq(band(opc1,11),11)} {band(opc3,1)} {eq(opc2,9)} UNDEFINED_CDP_CDP2_A1
# A7.6
#1111110(opcode:5)(Rn:4)(:4)101(:9) UNDEFINED_LDC2_STC2 # - handled by LDC2, STC2
[VFP1]110(opcode:5)(Rn:4)(:4)101(:9) [VFP2] {lt(opcode,2)} UNDEFINED
#[VFP1]110(opcode:5)(Rn:4)(:4)101(:9) [VFP2] {lt(opcode,4)} UNDEFINED # - (partially?) handled by VLDM/VSTM
#[VFP1]110(opcode:5)(Rn:4)(:4)101(:9) [VFP2] {eq(band(opcode,6),6)} UNDEFINED # - (partially?) handled by VLDM/VSTM
#[VFP1]110(opcode:5)(Rn:4)(:4)101(:9) [VFP2] {eq(band(opcode,0x1a),0x1a)} UNDEFINED # - (partially?) handled by VLDM/VSTM
# A7.8
#11111110(A:3)L(:8)101C(:1)(B:2)1(:4) UNDEFINED # - handled by MCR2, MRC2
[VFP1]1110(A:3)L(:8)101C(:1)(B:2)1(:4) [VFP2] {lnot(L)} {lnot(C)} {A} {ne(A,7)} UNDEFINED_MCR_MCR2_A1
[VFP1]1110(A:3)L(:8)101C(:1)(B:2)1(:4) [VFP2] {L} {lnot(C)} {A} {ne(A,7)} UNDEFINED_MRC_MRC2_A1
[VFP1]1110(A:3)L(:8)101C(:1)(B:2)1(:4) [VFP2] {lnot(L)} {C} {band(A,4)} {band(B,2)} UNDEFINED_MCR_MCR2_A1
# A7.9
#11111100010(:9)101C(op:4)(:4) UNDEFINED # - handled by MCRR2, MRRC2
[VFP1]11000100(:8)101C(op:4)(:4) [VFP2] {lnot(band(op,0xd))} UNDEFINED_MCRR_MCRR2_A1
[VFP1]11000101(:8)101C(op:4)(:4) [VFP2] {lnot(band(op,0xd))} UNDEFINED_MRRC_MRRC2_A1
[VFP1]11000100(:8)101C(op:4)(:4) [VFP2] {gt(op,3)} UNDEFINED_MCRR_MCRR2_A1
[VFP1]11000101(:8)101C(op:4)(:4) [VFP2] {gt(op,3)} UNDEFINED_MRRC_MRRC2_A1
# A8.8.280 VABS
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11101D110000(Vd:4)101(sz)11M0(Vm:4) [VFP2] VABS_A2 # NOTE: VFP vectors
# A8.8.283 VADD (floating-point)
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11100D11(Vn:4)(Vd:4)101(sz)N0M0(Vm:4) [VFP2] VADD_fp_A2 # NOTE: VFP vectors
# A8.8.303 VCMP, VCMPE
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11101D110100(Vd:4)101(sz)E1M0(Vm:4) [VFP2] VCMP_VCMPE_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11101D110101(Vd:4)101(sz)E1(0)0(0000) [VFP2] VCMP_VCMPE_A2
# A8.8.306 VCVT, VCVTR (between floating-point and integer, VFP)
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11101D111(opc2:3)(Vd:4)101(sz)(op)1M0(Vm:4) [VFP2] {lnot(land(opc2,ne(band(opc2,6),4)))} VCVT_VCVTR_fp_int_VFP_A1
# A8.8.308 VCVT (between floating-point and fixed-point, VFP)
# A1 VFPv3, VFPv4
[VFP1]11101D111(op)1U(Vd:4)101(sf)(sx)1i0(imm4:4) [VFP2] VCVT_fp_fx_VFP_A1
# A8.8.309 VCVT (between double-precitions and single-precision)
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11101D110111(Vd:4)101(sz)11M0(Vm:4) [VFP2] VCVT_dp_sp_A1
# A8.8.311 VCVTB, VCVTT (between half-precision and single-precision, VFP)
# A1 VFPv3, VFPv4
[VFP1]11101D11001(op)(Vd:4)101(0)T1M0(Vm:4) [VFP2] VCVTB_VCVTT_hp_sp_VFP_A1
# A8.8.312 VDIV
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11101D00(Vn:4)(Vd:4)101(sz)N0M0(Vm:4) [VFP2] VDIV_A1 # NOTE: VFP vectors
# A8.8.317 VFMA, VFMS
# A2 VFPv4
[VFP1]11101D10(Vn:4)(Vd:4)101(sz)N(op)M0(Vm:4) [VFP2] VFMA_VFMS_A2
# A8.8.318 VFNMA, VFNMS
# A1 VFPv4
[VFP1]11101D01(Vn:4)(Vd:4)101(sz)N(op)M0(Vm:4) [VFP2] VFNMA_VFNMS_A1
# A8.8.332 VLDM
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]110PUDW1(Rn:4)(Vd:4)1011(imm8:8) [VFP2] {lor(lor(P,U),W)} {lnot(land(land(lnot(P),U),land(W,eq(Rn,13))))} {lor(lnot(P),W)} VLDM_A1
[VFP1]110PUDW1(Rn:4)(Vd:4)1011(imm8:8) [VFP2] {eq(P,U)} {W} {ne(Rn,15)} UNDEFINED_LDC_LDC2_imm_A1 in VLDM_A1
[VFP1]110PUDW11111(Vd:4)1011(imm8:8) [VFP2] {eq(P,U)} {W} UNDEFINED_LDC_LDC2_lit_A1 in VLDM_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]110PUDW1(Rn:4)(Vd:4)1010(imm8:8) [VFP2] {lor(lor(P,U),W)} {lnot(land(land(lnot(P),U),land(W,eq(Rn,13))))} {lor(lnot(P),W)} VLDM_A2
[VFP1]110PUDW1(Rn:4)(Vd:4)1010(imm8:8) [VFP2] {eq(P,U)} {W} {ne(Rn,15)} UNDEFINED_LDC_LDC2_imm_A1 in VLDM_A2
[VFP1]110PUDW11111(Vd:4)1010(imm8:8) [VFP2] {eq(P,U)} {W} UNDEFINED_LDC_LDC2_lit_A1 in VLDM_A2
# A8.8.333 VLDR
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]1101UD01(Rn:4)(Vd:4)1011(imm8:8) [VFP2] VLDR_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]1101UD01(Rn:4)(Vd:4)1010(imm8:8) [VFP2] VLDR_A2
# A8.8.334 VMLA, VMLS (floating-point)
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11100D00(Vn:4)(Vd:4)101(sz)N(op)M0(Vm:4) [VFP2] VMLA_VMLS_fp_A2 # NOTE: VFP vectors
# A8.8.339 VMOV (immediate)
# A2 VFPv3, VFPv4
[VFP1]11101D11(imm4H:4)(Vd:4)101(sz)(0)0(0)0(imm4L:4) [VFP2] VMOV_imm_A2 # NOTE: VFP vectors
# A8.8.340 VMOV (register)
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11101D110000(Vd:4)101(sz)01M0(Vm:4) [VFP2] VMOV_reg_A2 # NOTE: VFP vectors
# A8.8.341 VMOV (ARM core register to scalar)
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]11100(opc1:2)0(Vd:4)(Rt:4)1011D(opc2:2)1(0000) [VFP2] VMOV_arm_A1
[VFP1]11100(opc1:2)0(Vd:4)(Rt:4)1011D(opc2:2)1(0000) [VFP2] {lnot(band(opc1,2))} {eq(opc2,2)} UNDEFINED_MCR_MCR2_A1 in VMOV_arm_A1
# A8.8.342 VMOV (scalar to ARM core register)
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]1110U(opc1:2)1(Vn:4)(Rt:4)1011N(opc2:2)1(0000) [VFP2] VMOV_scalar_A1
[VFP1]1110U(opc1:2)1(Vn:4)(Rt:4)1011N(opc2:2)1(0000) [VFP2] {lnot(band(opc1,2))} {lor(land(U,lnot(opc2)),eq(opc2,2))} UNDEFINED_MRC_MRC2_A1 in VMOV_scalar_A1
# A8.8.343 VMOV (betweem ARM core register and single-precition register)
# A1 VFPv2, VFPv3, VFPv4
[VFP1]1110000(op)(Vn:4)(Rt:4)1010N(00)1(0000) [VFP2] VMOV_1fp_A1
# A8.8.344 VMOV (between two ARM core registers and two single-precision registers)
# A1 VFPv2, VFPv3, VFPv4
[VFP1]1100010(op)(Rt2:4)(Rt:4)101000M1(Vm:4) [VFP2] VMOV_2fp_A1
# A8.8.345 VMOV (between two ARM core registers and a doubleword extension register)
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]1100010(op)(Rt2:4)(Rt:4)101100M1(Vm:4) [VFP2] VMOV_dbl_A1
# A8.8.348 VMRS
# A1 VFPv2, VFPv3, VFPv4, ASIMD
#[VFP1]111011110001(Rt:4)10100(00)1(0000) [VFP2] VMRS_A1 # - covered by B6.1.14 (ish - bit 7 is (0))
# A8.8.349 VMSR
# A1 VFPv2, VFPv3, VFPv4, ASIMD
#[VFP1]111011100001(Rt:4)10100(00)1(0000) [VFP2] VMSR_A1 # - covered by B6.1.15 (ish - bit 7 is (0))
# A8.8.351 VMUL (floating-point)
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11100D10(Vn:4)(Vd:4)101(sz)N0M0(Vm:4) [VFP2] VMUL_fp_A2 # NOTE: VFP vectors
# A8.8.355 VNEG
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11101D110001(Vd:4)101(sz)01M0(Vm:4) [VFP2] VNEG_A2 # NOTE: VFP vectors
# A8.8.356 VNMLA, VNMLS, VNMUL
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11100D01(Vn:4)(Vd:4)101(sz)N(op)M0(Vm:4) [VFP2] VNMLA_VNMLS_VNMUL_A1 # NOTE: VFP vectors
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11100D10(Vn:4)(Vd:4)101(sz)N1M0(Vm:4) [VFP2] VNMLA_VNMLS_VNMUL_A2 # NOTE: VFP vectors
# A8.8.367 VPOP
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]11001D111101(Vd:4)1011(imm8:8) [VFP2] VPOP_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11001D111101(Vd:4)1010(imm8:8) [VFP2] VPOP_A2
# A8.8.368 VPUSH
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]11010D101101(Vd:4)1011(imm8:8) [VFP2] VPUSH_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11010D101101(Vd:4)1010(imm8:8) [VFP2] VPUSH_A2
# A8.8.401 VSQRT
# A1 VFPv2, VFPv3, VFPv4
[VFP1]11101D110001(Vd:4)101(sz)11M0(Vm:4) [VFP2] VSQRT_A1 # NOTE: VFP vectors
# A8.8.412 VSTM
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]110PUDW0(Rn:4)(Vd:4)1011(imm8:8) [VFP2] {lor(lor(P,U),W)} {lnot(land(land(P,lnot(U)),land(W,eq(Rn,13))))} {lor(lnot(P),W)} VSTM_A1
[VFP1]110PUDW0(Rn:4)(Vd:4)1011(imm8:8) [VFP2] {eq(P,U)} {W} UNDEFINED_STC_STC2_A1 in VSTM_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]110PUDW0(Rn:4)(Vd:4)1010(imm8:8) [VFP2] {lor(lor(P,U),W)} {lnot(land(land(P,lnot(U)),land(W,eq(Rn,13))))} {lor(lnot(P),W)} VSTM_A2
[VFP1]110PUDW0(Rn:4)(Vd:4)1010(imm8:8) [VFP2] {eq(P,U)} {W} UNDEFINED_STC_STC2_A1 in VSTM_A2
# A8.8.413 VSTR
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]1101UD00(Rn:4)(Vd:4)1011(imm8:8) [VFP2] VSTR_A1
# A2 VFPv2, VFPv3, VFPv4
[VFP1]1101UD00(Rn:4)(Vd:4)1010(imm8:8) [VFP2] VSTR_A2
# A8.8.415 VSUB (floating-point)
# A2 VFPv2, VFPv3, VFPv4
[VFP1]11100D11(Vn:4)(Vd:4)101(sz)N1M0(Vm:4) [VFP2] VSUB_fp_A2 # NOTE: VFP vectors
# B9.3.14 VMRS
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]11101111(reg:4)(Rt:4)1010(000)1(0000) [VFP2] VMRS_A1
# B9.3.15 VMSR
# A1 VFPv2, VFPv3, VFPv4, ASIMD
[VFP1]11101110(reg:4)(Rt:4)1010(000)1(0000) [VFP2] VMSR_A1
Misc/decgen/encodings/ARMv7_nASIMD 0 → 100644
View file @ 30fe3ada
# Use:
# AS1(X)=1111001[X], AS2=11110100 for ARM
# AS1(X)=111[X]1111, AS2=11111001 for Thumb2
# A7.4
[AS1(U)](A:5)(:7)(B:4)(C:4)(:4) UNDEFINED
# A7.7
[AS2]A(:1)L0(:8)(B:4)(:8) UNDEFINED
Misc/decgen/encodings/ARMv7_nVFP 0 → 100644
View file @ 30fe3ada
# Use:
# VFP1=(cond:4) VFP2={ne(cond,15)} for ARM
# VFP1=1110 VFP2= for Thumb2
# A8.6.28 CDP, CDP2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]1110(opc1:4)(CRn:4)(CRd:4)(coproc:4)(opc2:3)0(CRm:4) [VFP2] {eq(band(coproc,14),10)} CDP_CDP2_A1
# A8.6.51 LDC, LDC2 (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]11000001(Rn:4)(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} {ne(Rn,15)} UNDEFINED
[VFP1]110PUDW1(Rn:4)(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} {ne(Rn,15)} {lor(lor(P,U),W)} LDC_LDC2_imm_A1
# A8.6.52 LDC, LDC2 (literal)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]110000011111(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} UNDEFINED
[VFP1]110PUDW11111(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} {lor(lor(P,U),W)} LDC_LDC2_lit_A1
# A8.6.92 MCR, MCR2
# A1 ARMv5TE*, ARMv6*, ARMv7
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]1110(opc1:3)0(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4) [VFP2] {eq(band(coproc,14),10)} MCR_MCR2_A1
# A8.6.93 MCRR, MCRR2
# A1 ARMv5TE*, ARMv6*, ARMv7
[VFP1]11000100(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4) [VFP2] {eq(band(coproc,14),10)} MCRR_MCRR2_A1
# A8.6.100 MRC, MRC2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]1110(opc1:3)1(CRn:4)(Rt:4)(coproc:4)(opc2:3)1(CRm:4) [VFP2] {eq(band(coproc,14),10)} MRC_MRC2_A1
# A8.6.101 MRRC, MRRC2
# A1 ARMv5TE*, ARMv6*, ARMv7
[VFP1]11000101(Rt2:4)(Rt:4)(coproc:4)(opc1:4)(CRm:4) [VFP2] {eq(band(coproc,14),10)} MRRC_MRRC2_A1
# A8.6.188 STC, STC2
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
[VFP1]11000000(Rn:4)(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} UNDEFINED
[VFP1]110PUDW0(Rn:4)(CRd:4)(coproc:4)(imm8:8) [VFP2] {eq(band(coproc,14),10)} {lor(lor(P,U),W)} STC_STC2_A1
Misc/decgen/encodings/FPA 0 → 100644
View file @ 30fe3ada
# From ARM7500FE datasheet
# Requires ARMv3/ARMv7 encoding file to be processed with:
# CDP={ne(coproc,1)}
# LDC_STC={ne(coproc,1)}{ne(coproc,2)}
# MRC_MCR={ne(coproc,1)}
# Use CC to restrict NV code (i.e. -DCC= for no restriction, -DCC={ne(cond,15)} for ARM restriction, -DCC={eq(cond,14)} for Thumb2 restriction)
# 10.1.1 LDF/STF
(cond:4)110P(UD)(T1)(Wb)(LS)(Rn:4)(T0)(Fd:3)0001(offset:8) [CC] {lor(P,Wb)} LDF_STF
(cond:4)110P(UD)(T1)(Wb)(LS)(Rn:4)(T0)(Fd:3)0001(offset:8) [CC] {lnot(lor(P,Wb))} UNDEFINED
# 10.1.3 LFM/SFM
(cond:4)110P(UD)(N1)(Wb)(LS)(Rn:4)(N0)(Fd:3)0010(offset:8) [CC] {lor(P,Wb)} LFM_SFM
(cond:4)110P(UD)(N1)(Wb)(LS)(Rn:4)(N0)(Fd:3)0010(offset:8) [CC] {lnot(lor(P,Wb))} UNDEFINED
# 10.2 Floating-Point Coprocessor Data Operations
(cond:4)1110(abcd:4)1(Fn:3)(j)(Fd:3)00011(gh:2)0(i)(Fm:3) [CC] UNDEFINED
(cond:4)11100000(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} ADF
(cond:4)11100001(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} MUF
(cond:4)11100010(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} SUF
(cond:4)11100011(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} RSF
(cond:4)11100100(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} DVF
(cond:4)11100101(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} RDF
(cond:4)11100110(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} POW
(cond:4)11100111(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} RPW
(cond:4)11101000(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} RMF
(cond:4)11101001(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} FML
(cond:4)11101010(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} FDV
(cond:4)11101011(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} FRD
(cond:4)11101100(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} POL
(cond:4)1110(abcd:4)(e)(Fn:3)0(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} {gt(abcd,12)} UNDEFINED
(cond:4)11100000(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} MVF
(cond:4)11100001(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} MNF
(cond:4)11100010(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} ABS
(cond:4)11100011(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} RND
(cond:4)11100100(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} SQT
(cond:4)11100101(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} LOG
(cond:4)11100110(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} LGN
(cond:4)11100111(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} EXP
(cond:4)11101000(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} SIN
(cond:4)11101001(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} COS
(cond:4)11101010(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} TAN
(cond:4)11101011(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} ASN
(cond:4)11101100(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} ACS
(cond:4)11101101(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} ATN
(cond:4)11101110(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} URD
(cond:4)11101111(e)(000)1(Fd:3)0001(f)(gh:2)0(i)(Fm:3) [CC] {lnot(land(e,f))} NRM
# 10.3 Floating-Point Coprocessor Register Transfer
(cond:4)11100000(e)(Fn:3)(Rd:4)0001(f)(gh:2)1(0)(000) [CC] {lnot(land(e,f))} FLT
(cond:4)11100000(e)(Fn:3)(Rd:4)0001(f)(gh:2)1(0)(000) [CC] {land(e,f)} UNDEFINED
(cond:4)11100001(0)(000)(Rd:4)0001(0)(gh:2)1(0)(Fm:3) [CC] FIX
(cond:4)11100010(0)(000)(Rd:4)0001(0)(00)1(0)(000) [CC] WFS
(cond:4)11100011(0)(000)(Rd:4)0001(0)(00)1(0)(000) [CC] RFS
(cond:4)11100100(0)(000)(Rd:4)0001(0)(00)1(0)(000) [CC] WFC
(cond:4)11100101(0)(000)(Rd:4)0001(0)(00)1(0)(000) [CC] RFC
(cond:4)1110011(LS)(0)(Fn:3)(Rd:4)0001(0)(00)1(i)(Fm:3) [CC] UNDEFINED
(cond:4)11101(bc:2)0(0)(Fn:3)(Rd:4)0001(0)(00)1(i)(Fm:3) [CC] UNDEFINED
# 10.3.1 Compare operations
(cond:4)11101001(0)(Fn:3)11110001(000)1(i)(Fm:3) [CC] CMF
(cond:4)11101011(0)(Fn:3)11110001(000)1(i)(Fm:3) [CC] CNF
(cond:4)11101101(0)(Fn:3)11110001(000)1(i)(Fm:3) [CC] CMFE
(cond:4)11101111(0)(Fn:3)11110001(000)1(i)(Fm:3) [CC] CNFE
# Undefined
(cond:4)11101(cd:2)1(e)(Fn:3)(Rd:4)0001(fgh:3)1(i)(Fm:3) [CC] {ne(Rd,15)} UNDEFINED # Compare with Rd!=15
Misc/decgen/encodings/XScale_DSP 0 → 100644
View file @ 30fe3ada
# From the XScale developer's manual
# Can be overlaid directly ontop of the ARMv7 encodings
# Note that most/all XScales only support acc=0; behaviour is unpredictable for other values
# Table 2-1, Multiply with Internal Accumulate
(cond:4)11100010(opcode_3:4)(Rs:4)0000(acc:3)1(Rm:4) {ne(cond,15)} UNPREDICTABLE_DSP in MCR_MCR2_A1
(cond:4)11100010(opcode_3:4)(Rs:4)0000(acc:3)1(Rm:4) {ne(cond,15)} {eq(opcode_3,0)} MIA in UNPREDICTABLE_DSP
(cond:4)11100010(opcode_3:4)(Rs:4)0000(acc:3)1(Rm:4) {ne(cond,15)} {eq(opcode_3,8)} MIAPH in UNPREDICTABLE_DSP
(cond:4)1110001011xy(Rs:4)0000(acc:3)1(Rm:4) {ne(cond,15)} MIAxy in UNPREDICTABLE_DSP
# Table 2-5, Internal Accumulator Access
(cond:4)1100010L(RdHi:4)(RdLo:4)0000(0000)(0)(acc:3) {ne(cond,15)} {lnot(L)} MAR in MCRR_MCRR2_A1
(cond:4)1100010L(RdHi:4)(RdLo:4)0000(0000)(0)(acc:3) {ne(cond,15)} {L} MRA in MRRC_MRRC2_A1
VersionNum
View file @ 30fe3ada
/* (1.64)
/* (1.65)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.64
#define Module_MajorVersion_CMHG 1.65
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 30 Jul 2013
#define Module_Date_CMHG 28 Nov 2013
#define Module_MajorVersion "1.64"
#define Module_Version 164
#define Module_MajorVersion "1.65"
#define Module_Version 165
#define Module_MinorVersion ""
#define Module_Date "30 Jul 2013"
#define Module_Date "28 Nov 2013"
#define Module_ApplicationDate "30-Jul-13"
#define Module_ApplicationDate "28-Nov-13"
#define Module_ComponentName "Library"
#define Module_ComponentPath "mixed/RiscOS/Library"
#define Module_FullVersion "1.64"
#define Module_HelpVersion "1.64 (30 Jul 2013)"
#define Module_LibraryVersionInfo "1:64"
#define Module_FullVersion "1.65"
#define Module_HelpVersion "1.65 (28 Nov 2013)"
#define Module_LibraryVersionInfo "1:65"
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