Commit 21ff3d72 authored by Robert Sprowson's avatar Robert Sprowson
Browse files

Add the later ARMv8 AArch32 opcodes

ARM have added SETPAN, ESB, TSB, CSDB, PSSBB, SSBB since the earlier ARM ARM that the decgen encodings were based on.
Add these, update the page references from the newer ARM ARM, and make some holes in the ARMv7 encoding to accommodate.

Version 1.97. Tagged as 'Library-1_97'
parent 742c9bef
......@@ -15,7 +15,8 @@
(cond:4)0001(op:4)(:12)1001(:4) {ne(cond,15)} {lt(op,8)} {band(op,3)} UNDEFINED
# A5.2.11
(cond:4)00110(op)10(op1:4)(:8)(op2:8) {ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,5)} {lt(op2,0xf0)} UNALLOCATED_HINT
# > SEVL != ESB != TSB != CSDB < DBG
(cond:4)00110(op)10(op1:4)(:8)(op2:8) {ne(cond,15)} {lnot(op)} {lnot(op1)} {gt(op2,5)} {land(land(ne(op2,16),ne(op2,18)),ne(op2,20))} {lt(op2,0xf0)} UNALLOCATED_HINT
# A5.2.12
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,1)} {lnot(band(op,1))} UNDEFINED
......@@ -68,7 +69,8 @@
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {lt(op1,16)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(op1,16)} {lnot(band(Rn,1))} {band(op2,2)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(op1,16)} {band(Rn,1)} {op2} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {gt(op1,16)} {lt(op1,32)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(op1,17)} {op2} UNDEFINED # See SETPAN when op2 zero
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {gt(op1,17)} {lt(op1,32)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(band(op1,0x77),0x41)} UNALLOCATED_MEM_HINT
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(band(op1,0x77),0x50)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(band(op1,0x77),0x51)} {eq(Rn,15)} UNPREDICTABLE
......@@ -80,7 +82,6 @@
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(band(op1,0x61),0x61)} {band(op2,1)} UNDEFINED
11110(op1:7)(Rn:4)(:8)(op2:4)(:4) {eq(band(op1,0x63),0x63)} {lnot(band(op2,1))} UNPREDICTABLE
# A8.8.1 ADC (immediate)
# A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
(cond:4)0010101S(Rn:4)(Rd:4)(imm12:12) {ne(cond,15)} ADC_imm_A1 # NOTE: Action must handle "SUBS PC, LR and related instructions"
......
# From DDI 0487A.g section J5
# From DDI 0487D.b
# Can be overlaid directly on top of the ARMv7 encodings
# F6.1.54 Load-Aquire
# F5.1.57 Load-Aquire
(cond:4)00011(sz:2)1(Rn:4)(Rt:4)(11)001001(1111) {ne(cond,15)} {ne(sz,1)} LDA_A1
# F6.1.210 Store-Release
# F5.1.216 Store-Release
(cond:4)00011(sz:2)0(Rn:4)(1111)(11)001001(Rt:4) {ne(cond,15)} {ne(sz,1)} STL_A1
# F6.1.56 Load-Aquire Exclusive
# F5.1.59 Load-Aquire Exclusive
(cond:4)00011001(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEX_A1
(cond:4)00011011(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXD_A1
(cond:4)00011101(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXB_A1
(cond:4)00011111(Rn:4)(Rt:4)(11)101001(1111) {ne(cond,15)} LDAEXH_A1
# F6.1.212 Store-Release Exclusive
# F5.1.218 Store-Release Exclusive
(cond:4)00011000(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEX_A1
(cond:4)00011010(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXD_A1
(cond:4)00011100(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXB_A1
(cond:4)00011110(Rn:4)(Rd:4)(11)101001(Rt:4) {ne(cond,15)} STLEXH_A1
# Table J5.7.1 External Debug
# Table H2.4.6 External Debug
# DCPS1/2/3 has no A32 encoding
# F6.1.50 Halting breakpoint
# F5.1.53 Halting breakpoint
(cond:4)00010(op:2)0(imm12:12)0(op2:3)(imm4:4) {ne(cond,15)} {eq(op2,7)} {lnot(op)} HLT_A1
# Table J5.7.2 Barriers and hints
# Barriers and hints
# DMB OSHLD/NSHLD/ISHLD/LD see F6.1.44, same encoding as ARMv7
# DSB OSHLD/NSHLD/ISHLD/LD see F6.1.45, same encoding as ARMv7
# PSSBB see F5.1.141, ARMv8.4, encoded in DSB space as per ARMv7
# SSBB see F5.1.212, ARMv8.4, encoded in DSB space as per ARMv7
# F6.1.179 Send event local
# F5.1.184 Send event local
(cond:4)001100100000(11110000)00000101 {ne(cond,15)} SEVL_A1
# Table J5.7.3 TLB maintenance
# Accessed using MCR operations, so no new opcodes
# F5.1.52 Error sync barrier
# ARMv8.2
(cond:4)001100100000(11110000)00010000 {ne(cond,15)} ESB_A1
# F6.1.40 CRC
# F5.1.260 Trace sync barrier
# ARMv8.4
(cond:4)001100100000(11110000)00010010 {ne(cond,15)} TSB_A1
# F5.1.41 Consumption of speculative data barrier
# ARMv8.4
(cond:4)001100100000(11110000)00010100 {ne(cond,15)} CSDB_A1
# F5.1.182 SETPAN
# ARMv8.1
111100010001(0000000000)I(0)0000(0000) SETPAN_A1
# F5.1.39 CRC
(cond:4)00010(sz:2)0(Rn:4)(Rd:4)(0)(0)C(0)0(op2:3)(Rm:4) {ne(cond,15)} {eq(op2,4)} CRC_A1
# Note that [LDR|STR]EX[B|H|D] appear here because previously
# bits 8-11 SBO, but that recommendation has changed because
# ARMv8 has added [LDA|STL]EX[B|H|D] in the same instruction space.
# F4.2.10
# F4.1.3
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {lor(eq(op,8),eq(op,9))} {eq(op1,1)} UNDEFINED
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {lor(eq(op,10),eq(op,11))} {lnot(band(op1,2))} UNDEFINED
(cond:4)0001(op:4)(:8)(11)(op1:2)1001(:4) {ne(cond,15)} {ge(op,12)} {eq(op1,1)} UNDEFINED
......
# From DDI 0487A.g section J5
# From DDI 0487D.b
# Overlay this with ARMv7 encodings to fill the holes where ARMv8 additions are
# F6.1.54 Load-Aquire
# F6.1.210 Store-Release
# F6.1.56 Load-Aquire Exclusive
# F6.1.212 Store-Release Exclusive
# F5.1.57 Load-Aquire
# F5.1.216 Store-Release
# F5.1.59 Load-Aquire Exclusive
# F5.1.218 Store-Release Exclusive
# These alias into the LDREX/STREX family (see below)
# F6.1.50 Halting breakpoint
# F5.1.53 Halting breakpoint
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,7)} {lnot(op)} UNDEFINED
# F6.1.179 Send event local
# F5.1.184 Send event local
(cond:4)001100100000(11110000)00000101 {ne(cond,15)} UNALLOCATED_MEM_HINT
# F6.1.40 CRC
# F5.1.52 Error sync barrier
(cond:4)001100100000(11110000)00010000 {ne(cond,15)} UNALLOCATED_MEM_HINT
# F5.1.260 Trace sync barrier
(cond:4)001100100000(11110000)00010010 {ne(cond,15)} UNALLOCATED_MEM_HINT
# F5.1.41 Consumption of speculative data barrier
(cond:4)001100100000(11110000)00010100 {ne(cond,15)} UNALLOCATED_MEM_HINT
# F5.1.182 SETPAN
111100010001(0000000000)(:1)(0)0000(0000) UNDEFINED
# F5.1.39 CRC
(cond:4)00010(op:2)0(op1:4)(:8)0(op2:3)(:4) {ne(cond,15)} {eq(op2,4)} UNDEFINED
# Note that [LDR|STR]EX[B|H|D] appear here because previously
......
/* (1.96)
/* (1.97)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 1.96
#define Module_MajorVersion_CMHG 1.97
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 23 May 2019
#define Module_Date_CMHG 06 Jul 2019
#define Module_MajorVersion "1.96"
#define Module_Version 196
#define Module_MajorVersion "1.97"
#define Module_Version 197
#define Module_MinorVersion ""
#define Module_Date "23 May 2019"
#define Module_Date "06 Jul 2019"
#define Module_ApplicationDate "23-May-19"
#define Module_ApplicationDate "06-Jul-19"
#define Module_ComponentName "Library"
#define Module_FullVersion "1.96"
#define Module_HelpVersion "1.96 (23 May 2019)"
#define Module_LibraryVersionInfo "1:96"
#define Module_FullVersion "1.97"
#define Module_HelpVersion "1.97 (06 Jul 2019)"
#define Module_LibraryVersionInfo "1:97"
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