Commit 9b78d05f authored by Ben Avison's avatar Ben Avison
Browse files

Support for ARMv8

Detail:
  The SWP and SWPB instructions have finally been removed in ARMv8, after
  having been deprecated for a very long time. This version adds alternative
  versions of code that used to use them with ones that use LDREX/STREX and
  LDREXB/STREXB instead. Soft-loadable C libraries will choose between
  implementations at runtime using OS_PlatformFeatures; ROM builds only
  include the appropriate version for the target hardware.
Admin:
  Tested on Raspberry Pi 3.

Version 5.88. Tagged as 'RISC_OSLib-5_88'
parent 2d80a05a
...@@ -11,13 +11,13 @@ ...@@ -11,13 +11,13 @@
GBLS Module_HelpVersion GBLS Module_HelpVersion
GBLS Module_ComponentName GBLS Module_ComponentName
GBLS Module_ComponentPath GBLS Module_ComponentPath
Module_MajorVersion SETS "5.87" Module_MajorVersion SETS "5.88"
Module_Version SETA 587 Module_Version SETA 588
Module_MinorVersion SETS "" Module_MinorVersion SETS ""
Module_Date SETS "13 Feb 2016" Module_Date SETS "29 Feb 2016"
Module_ApplicationDate SETS "13-Feb-16" Module_ApplicationDate SETS "29-Feb-16"
Module_ComponentName SETS "RISC_OSLib" Module_ComponentName SETS "RISC_OSLib"
Module_ComponentPath SETS "castle/RiscOS/Sources/Lib/RISC_OSLib" Module_ComponentPath SETS "castle/RiscOS/Sources/Lib/RISC_OSLib"
Module_FullVersion SETS "5.87" Module_FullVersion SETS "5.88"
Module_HelpVersion SETS "5.87 (13 Feb 2016)" Module_HelpVersion SETS "5.88 (29 Feb 2016)"
END END
/* (5.87) /* (5.88)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 5.87 #define Module_MajorVersion_CMHG 5.88
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 13 Feb 2016 #define Module_Date_CMHG 29 Feb 2016
#define Module_MajorVersion "5.87" #define Module_MajorVersion "5.88"
#define Module_Version 587 #define Module_Version 588
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "13 Feb 2016" #define Module_Date "29 Feb 2016"
#define Module_ApplicationDate "13-Feb-16" #define Module_ApplicationDate "29-Feb-16"
#define Module_ComponentName "RISC_OSLib" #define Module_ComponentName "RISC_OSLib"
#define Module_ComponentPath "castle/RiscOS/Sources/Lib/RISC_OSLib" #define Module_ComponentPath "castle/RiscOS/Sources/Lib/RISC_OSLib"
#define Module_FullVersion "5.87" #define Module_FullVersion "5.88"
#define Module_HelpVersion "5.87 (13 Feb 2016)" #define Module_HelpVersion "5.88 (29 Feb 2016)"
#define Module_LibraryVersionInfo "5:87" #define Module_LibraryVersionInfo "5:88"
...@@ -250,28 +250,37 @@ static char sys_message[60]; ...@@ -250,28 +250,37 @@ static char sys_message[60];
static int heapMutex; static int heapMutex;
extern int _swp_available; extern int _swp_available;
#define INITMUTEX heapMutex = 1
#ifndef __APCS_32 #ifndef __APCS_32
static int arm2_swp(int newValue, int *location); static int arm2_swp(int newValue, int *location);
#endif
static inline int swp(int newValue, int *location) static inline int swp(int newValue, int *location)
{ {
#ifndef __APCS_32
if (!_swp_available) return arm2_swp(newValue, location); if (!_swp_available) return arm2_swp(newValue, location);
#endif
int oldValue; int oldValue;
__asm { SWP oldValue, newValue, [location] } __asm { SWP oldValue, newValue, [location] }
return oldValue; return oldValue;
} }
#define INITMUTEX heapMutex = 1
#define ACQUIREMUTEX \ #define ACQUIREMUTEX \
do { \ do { \
while (swp(0, &heapMutex) == 0) \ while (swp(0, &heapMutex) == 0) \
_swix(OS_UpCall, _INR(0,1), 6, &heapMutex); \ _swix(OS_UpCall, _INR(0,1), 6, &heapMutex); \
} while (0) } while (0)
#else
extern void AcquireMutex(volatile int *p);
#define ACQUIREMUTEX \
do { \
AcquireMutex(&heapMutex); \
} while (0)
#endif
#define RELEASEMUTEX { heapMutex = 1; } #define RELEASEMUTEX { heapMutex = 1; }
#define RELEASEANDRETURN(value) {RELEASEMUTEX return (value);} #define RELEASEANDRETURN(value) {RELEASEMUTEX return (value);}
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
GET h_stack.s GET h_stack.s
GET h_workspc.s GET h_workspc.s
GET Hdr:OSMisc
EXPORT |_kernel_exit| EXPORT |_kernel_exit|
EXPORT |_kernel_setreturncode| EXPORT |_kernel_setreturncode|
...@@ -102,6 +103,7 @@ ...@@ -102,6 +103,7 @@
EXPORT |x$uremainder| EXPORT |x$uremainder|
EXPORT |__counter| EXPORT |__counter|
EXPORT |AcquireMutex|
PSRBits * &FC000003 PSRBits * &FC000003
PSRZBit * &40000000 PSRZBit * &40000000
...@@ -411,8 +413,21 @@ uwb_size # 0 ...@@ -411,8 +413,21 @@ uwb_size # 0
; not IsAStackChunk) and SL_xxx_Offset. Also prev. ; not IsAStackChunk) and SL_xxx_Offset. Also prev.
STR sp, [v6, #O_extendChunk] STR sp, [v6, #O_extendChunk]
[ {CONFIG}<>26 [ {CONFIG}<>26
MOV r0, #1 MOV r0, #OSPlatformFeatures_ReadCodeFeatures
STR r0, [v6, #O__swp_available] SWI XOS_PlatformFeatures
MOVVS r0, #0
; _swp_available is used as a bitfield:
; bit 0 => SWP available
; bit 1 => LDREX/STREX available
; bit 2 => LDREX[B|D|H]/STREX[B|D|H] available
; This is a simple manipulation of the PlatformFeatures return flags
ASSERT CPUFlag_NoSWP = 1:SHL:11
ASSERT CPUFlag_LoadStoreEx = 1:SHL:12
ASSERT CPUFlag_LoadStoreClearExSizes = 1:SHL:13
EOR r0, r0, #CPUFlag_NoSWP
MOV r1, #7
AND r1, r1, r0, LSR #11
STR r1, [v6, #O__swp_available]
| |
BL CheckIfSwpAvailable BL CheckIfSwpAvailable
] ]
...@@ -1615,10 +1630,26 @@ ErrorHandler Keep ...@@ -1615,10 +1630,26 @@ ErrorHandler Keep
MOVS pc, a4 MOVS pc, a4
| |
LoadStaticBase a3 LoadStaticBase a3
[ SupportARMK :LAND: NoARMK
LDR a4, [a3, #O__swp_available]
TST a4, #4 ; CPU supports LDREXB?
]
MOV a2, #0 MOV a2, #0
ADD a3, a3, #O_escapeSeen :AND: :NOT: &FF ADD a3, a3, #O_escapeSeen :AND: :NOT: &FF
ADD a3, a3, #O_escapeSeen :AND: &FF ; Yuckeroo ADD a3, a3, #O_escapeSeen :AND: &FF ; Yuckeroo
[ SupportARMK
[ NoARMK
SWPEQB a1, a2, [a3]
BEQ %FT02
]
01 LDREXB a1, [a3]
STREXB a4, a2, [a3]
TEQ a4, #1
BEQ %BT01
02
|
SWPB a1, a2, [a3] SWPB a1, a2, [a3]
]
Return "", LinkNotStacked Return "", LinkNotStacked
] ]
...@@ -2933,7 +2964,22 @@ StkOvfGetNewChunk Keep ...@@ -2933,7 +2964,22 @@ StkOvfGetNewChunk Keep
SWPNE a1, a1, [a2] SWPNE a1, a1, [a2]
BLEQ Arm2Swp BLEQ Arm2Swp
| |
[ SupportARMv6
[ NoARMv6
LDR lr, [v2, #O__swp_available]
TST lr, #2 ; CPU supports LDREX?
SWPEQ a1, a1, [a2]
BEQ %FT02
]
MOV lr, #0
01 LDREXB a1, [a2]
STREXB a3, lr, [a2]
TEQ a3, #1
BEQ %BT01
02
|
SWP a1, a1, [a2] SWP a1, a1, [a2]
]
] ]
TEQ a1, #0 TEQ a1, #0
BLEQ Sleep ; preserves Z BLEQ Sleep ; preserves Z
...@@ -3029,6 +3075,41 @@ Arm2Swp ; like SWP a1,a1,[a2] but corrupts a3, lr and flags ...@@ -3029,6 +3075,41 @@ Arm2Swp ; like SWP a1,a1,[a2] but corrupts a3, lr and flags
SWI IntOn SWI IntOn
MOV a1, a3 MOV a1, a3
MOV pc, lr MOV pc, lr
|
AcquireMutex
FunctionEntry
MOV a2, a1
[ SupportARMv6
[ NoARMv6
LoadStaticBase a4, ip
LDR a1, [a4, #O__swp_available]
TST a1, #2 ; does CPU support LDREX?
BEQ %FT03
]
MOV a3, #0
]
B %FT02
[ SupportARMv6
01 MOV a1, #6
SWI XOS_UpCall
02 LDREX a1, [a2]
STREX a4, a3, [a2]
TEQ a4, #1
BEQ %BT02
TEQ a1, #0
BEQ %BT01
Return
]
[ NoARMv6
01 MOV a1, #6
SWI XOS_UpCall
02
03 MOV a1, #0
SWP a1, a1, [a2]
TEQ a1, #0
BEQ %BT01
Return
]
] ]
Sleep Sleep
......
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