Commit e6c4e3c2 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Fix global OS_SynchroniseCodeAreas. ARMop tweaks.

Detail:
  s/ExtraSWIs - Fix global OS_SynchroniseCodeAreas using the wrong appspace size; would have resulted in appspace only being partially synced if some pages were mapped out due to lazy swapping
  s/ARMops, s/ExtraSWIs, s/MemMap2 - Simplify code by making DCache_LineLen / ICache_LineLen store the actual line length values on ARMv7+ instead of the log2 values. Optimise SMP I-cache invalidation by allowing it to do a global invalidate. Ensure all ARMv7+ range checks use LO instead of NE, to avoid any problems with mismatched I/D line lengths (can't be sure the op range was rounded to the larger of the two)
Admin:
  Tested on iMX6


Version 5.88, 4.129.2.5. Tagged as 'Kernel-5_88-4_129_2_5'
parent aa71a49c
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.88"
Module_Version SETA 588
Module_MinorVersion SETS "4.129.2.4"
Module_Date SETS "31 Aug 2017"
Module_ApplicationDate SETS "31-Aug-17"
Module_MinorVersion SETS "4.129.2.5"
Module_Date SETS "03 Sep 2017"
Module_ApplicationDate SETS "03-Sep-17"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.88 (4.129.2.4)"
Module_HelpVersion SETS "5.88 (31 Aug 2017) 4.129.2.4"
Module_FullVersion SETS "5.88 (4.129.2.5)"
Module_HelpVersion SETS "5.88 (03 Sep 2017) 4.129.2.5"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.88
#define Module_MinorVersion_CMHG 4.129.2.4
#define Module_Date_CMHG 31 Aug 2017
#define Module_MinorVersion_CMHG 4.129.2.5
#define Module_Date_CMHG 03 Sep 2017
#define Module_MajorVersion "5.88"
#define Module_Version 588
#define Module_MinorVersion "4.129.2.4"
#define Module_Date "31 Aug 2017"
#define Module_MinorVersion "4.129.2.5"
#define Module_Date "03 Sep 2017"
#define Module_ApplicationDate "31-Aug-17"
#define Module_ApplicationDate "03-Sep-17"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.88 (4.129.2.4)"
#define Module_HelpVersion "5.88 (31 Aug 2017) 4.129.2.4"
#define Module_FullVersion "5.88 (4.129.2.5)"
#define Module_HelpVersion "5.88 (03 Sep 2017) 4.129.2.5"
#define Module_LibraryVersionInfo "5:88"
This diff is collapsed.
......@@ -231,12 +231,7 @@ SyncCodeAreasRange
MOV r0, r1
ADD r1, r2, #4 ;exclusive end address
LDR r2, =ZeroPage
LDRB lr, [r2, #Cache_Type]
CMP lr, #CT_ctype_WB_CR7_Lx ; DCache_LineLen lin or log?
LDRB lr, [r2, #DCache_LineLen]
MOVEQ r2, #4
MOVEQ lr, r2, LSL lr
LDREQ r2, =ZeroPage
SUB lr, lr, #1
ADD r1, r1, lr ;rounding up end address
MVN lr, lr
......@@ -252,13 +247,9 @@ SyncCodeAreasFull
ARMop Cache_RangeThreshold,,,r2
CMP r0, #-1
BNE %FT90
; ARMops are in SMP-friendly mode
; ARMops are in SMP-friendly mode, which means we have no (SMP-friendly) global IMB available
; Just clean application space and the RMA?
GetAppSpaceDANode r1, r2
LDR r0, [r1, #DANode_Flags]
TST r0, #DynAreaFlags_PMP
LDR r1, [r1, #DANode_Size]
ADDNE r1, r1, #32*1024
LDR r1, [r2, #AplWorkSize]
MOV r0, #32*1024
ARMop IMB_Range,,,r2
MOV r0, #ChangeDyn_RMA
......
......@@ -597,11 +597,7 @@ AdjustMemoryPageFlags ROUT
; BangCamUpdate won't have done anything useful.
; So start by flushing the L2PT word from the cache.
ADD r0, r8, r3, LSR #10 ; -> L2PT entry we modified
LDRB r2, [r12, #Cache_Type]
CMP r2, #CT_ctype_WB_CR7_Lx ; DCache_LineLen lin or log?
LDRB r2, [r12, #DCache_LineLen]
MOVEQ lr, #4
MOVEQ r2, lr, LSL r2
SUB r2, r2, #1
BIC r0, r0, r2
ADD r1, r0, r2
......
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