From e2262380d285ec382971f4b92f6e49cc1180204a Mon Sep 17 00:00:00 2001
From: Jeffrey Lee <jlee@gitlab.riscosopen.org>
Date: Sun, 1 Feb 2009 13:25:06 +0000
Subject: [PATCH] Initial kernel support for Cortex-A8 processors.
Detail:
hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
hdr/Options - Enabled various kernel debug options
s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
s/NewIRQs - Increase MaxInterrupts to 96
Admin:
Brief testing under qemu-omap3.
Version 5.35, 4.79.2.98.2.1. Tagged as 'Kernel-5_35-4_79_2_98_2_1'
---
VersionASM | 10 +++++-----
VersionNum | 14 +++++++-------
hdr/ARMops | 2 ++
hdr/Options | 10 +++++-----
s/ARMops | 11 ++++++++++-
s/NewIRQs | 2 +-
6 files changed, 30 insertions(+), 19 deletions(-)
diff --git a/VersionASM b/VersionASM
index cdc3deb..550716f 100644
--- a/VersionASM
+++ b/VersionASM
@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
-Module_MinorVersion SETS "4.79.2.98"
-Module_Date SETS "22 Dec 2008"
-Module_ApplicationDate SETS "22-Dec-08"
+Module_MinorVersion SETS "4.79.2.98.2.1"
+Module_Date SETS "01 Feb 2009"
+Module_ApplicationDate SETS "01-Feb-09"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
-Module_FullVersion SETS "5.35 (4.79.2.98)"
-Module_HelpVersion SETS "5.35 (22 Dec 2008) 4.79.2.98"
+Module_FullVersion SETS "5.35 (4.79.2.98.2.1)"
+Module_HelpVersion SETS "5.35 (01 Feb 2009) 4.79.2.98.2.1"
END
diff --git a/VersionNum b/VersionNum
index 56b3d8b..abdf808 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
-#define Module_MinorVersion_CMHG 4.79.2.98
-#define Module_Date_CMHG 22 Dec 2008
+#define Module_MinorVersion_CMHG 4.79.2.98.2.1
+#define Module_Date_CMHG 01 Feb 2009
#define Module_MajorVersion "5.35"
#define Module_Version 535
-#define Module_MinorVersion "4.79.2.98"
-#define Module_Date "22 Dec 2008"
+#define Module_MinorVersion "4.79.2.98.2.1"
+#define Module_Date "01 Feb 2009"
-#define Module_ApplicationDate "22-Dec-08"
+#define Module_ApplicationDate "01-Feb-09"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
-#define Module_FullVersion "5.35 (4.79.2.98)"
-#define Module_HelpVersion "5.35 (22 Dec 2008) 4.79.2.98"
+#define Module_FullVersion "5.35 (4.79.2.98.2.1)"
+#define Module_HelpVersion "5.35 (01 Feb 2009) 4.79.2.98.2.1"
#define Module_LibraryVersionInfo "5:35"
diff --git a/hdr/ARMops b/hdr/ARMops
index 2efdc14..57fb262 100644
--- a/hdr/ARMops
+++ b/hdr/ARMops
@@ -19,6 +19,7 @@ ARMv4T * 2
ARMv5 * 3
ARMv5T * 4
ARMv5TE * 5
+ARMvF * &F ; 'Fancy' ARM that describes its features in the feature registers
^ 0
ARM600 # 1
@@ -37,6 +38,7 @@ ARM920T # 1
ARM922T # 1
X80200 # 1
X80321 # 1
+Cortex_A8 # 1
ARMunk * 255
; These flags are stored in ProcessorFlags and returned by OS_PlatformFeatures 0 (Read code features)
diff --git a/hdr/Options b/hdr/Options
index c2b19db..95318d9 100644
--- a/hdr/Options
+++ b/hdr/Options
@@ -90,7 +90,7 @@ ParallelFlashUpgrade SETL {FALSE}
;whether we support running on the (Risc PC) emulator
GBLL EmulatorSupport
-EmulatorSupport SETL {TRUE}
+EmulatorSupport SETL {FALSE} ; Disabled; QEMU doesn't like it
[ :LNOT: RO371Timings
@@ -302,19 +302,19 @@ RMTidyDoesNowt SETL {TRUE} ; should really be "machine has
RogerEXEY SETL {FALSE} ; Marketing don't like it!
GBLL DebugROMInit
-DebugROMInit SETL {FALSE}
+DebugROMInit SETL {TRUE}
GBLL DebugROMPostInit ; Displays when the PostInit service call is sent to each ROM module (currently works on vanilla service call handling only)
DebugROMPostInit SETL (:LNOT: ChocolateService) :LAND: {FALSE}
GBLL DebugROMErrors
-DebugROMErrors SETL {FALSE}
+DebugROMErrors SETL {TRUE}
GBLL DebugTerminal ; default WRCH and RDCH through HAL
-DebugTerminal SETL {FALSE}
+DebugTerminal SETL {TRUE}
GBLL DebugHALTX
-DebugHALTX SETL {FALSE}
+DebugHALTX SETL {TRUE}
GBLL DebugHeaps ; initialise claimed and freed blocks
DebugHeaps SETL {FALSE} ; (may slow things down unacceptably)
diff --git a/s/ARMops b/s/ARMops
index e8e27f7..3b6c1fd 100644
--- a/s/ARMops
+++ b/s/ARMops
@@ -64,7 +64,11 @@ Init_ARMarch
ARM_Analyse
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
- ARM_read_cachetype v2
+ ; New ARMs have a cache type register that doesn't match the format we expect
+ BL Init_ARMarch
+ CMP a1, #ARMvF
+ MOVEQ v2, v1 ; New ARM; set v2=v1 to enable table lookup
+ ARM_read_cachetype v2,NE ; Old ARM; read directly
MOV v6, #ZeroPage
ADRL v7, KnownCPUTable
@@ -612,6 +616,7 @@ KnownCPUTable
CPUDesc ARM922T, &029220, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 8K, 64, 8, 8K, 64, 8
CPUDesc X80200, &052000, &0FFFF0, ARMv5TE, WB_Cal_LD, 1, 32K, 32, 8, 32K, 32, 8
CPUDesc X80321, &69052400, &FFFFF700, ARMv5TE, WB_Cal_LD, 1, 32K, 32, 8, 32K, 32, 8
+ CPUDesc Cortex_A8, &00C080, &00FFF0, ARMv5TE, WB_CR7_LDa, 1, 16K, 32, 16, 16K, 32, 16
DCD -1
@@ -634,6 +639,7 @@ KnownCPUFlags
DCD 0, 0 ; ARM 922T
DCD CPUFlag_ExtendedPages+CPUFlag_XScale, 0 ; X80200
DCD CPUFlag_XScale, 0 ; X80321
+ DCD 0, 0 ; Cortex_A8
; --------------------------------------------------------------------------
; ----- ARMops -------------------------------------------------------------
@@ -1618,6 +1624,7 @@ PNameTable
DCW PName_ARM922T - PNameTable
DCW PName_X80200 - PNameTable
DCW PName_X80321 - PNameTable
+ DCW PName_Cortex_A8 - PNameTable
PName_ARM600
= "600:ARM 600 Processor",0
@@ -1649,6 +1656,8 @@ PName_X80200
= "X80200:80200 Processor",0
PName_X80321
= "X80321:80321 Processor",0
+PName_Cortex_A8
+ = "CortexA8:Cortex-A8 Processor",0
ALIGN
diff --git a/s/NewIRQs b/s/NewIRQs
index e935f6d..36b43b2 100644
--- a/s/NewIRQs
+++ b/s/NewIRQs
@@ -205,7 +205,7 @@ DefaultIRQ1Vcode_end
Devices * DefaultIRQ1Vcode_end + 12
NoInterrupt * -1
-MaxInterrupts * 64
+MaxInterrupts * 96
DevicesEnd * Devices + MaxInterrupts * 12
--
GitLab