Commit b375500e authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Fix inverted global vs. per-page cache flush logic in PMP LogOp_MapOut

Detail:
  s/ChangeDyn - Set r6 bit 0 if the area is smaller than the cache range threshold, because that's what's checked for at lines 3077 and 3092
Admin:
  Tested on Raspberry Pi


Version 5.76. Tagged as 'Kernel-5_76'
parent 06079048
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.75"
Module_Version SETA 575
Module_MajorVersion SETS "5.76"
Module_Version SETA 576
Module_MinorVersion SETS ""
Module_Date SETS "17 Dec 2016"
Module_ApplicationDate SETS "17-Dec-16"
Module_Date SETS "11 Jan 2017"
Module_ApplicationDate SETS "11-Jan-17"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.75"
Module_HelpVersion SETS "5.75 (17 Dec 2016)"
Module_FullVersion SETS "5.76"
Module_HelpVersion SETS "5.76 (11 Jan 2017)"
END
/* (5.75)
/* (5.76)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 5.75
#define Module_MajorVersion_CMHG 5.76
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 17 Dec 2016
#define Module_Date_CMHG 11 Jan 2017
#define Module_MajorVersion "5.75"
#define Module_Version 575
#define Module_MajorVersion "5.76"
#define Module_Version 576
#define Module_MinorVersion ""
#define Module_Date "17 Dec 2016"
#define Module_Date "11 Jan 2017"
#define Module_ApplicationDate "17-Dec-16"
#define Module_ApplicationDate "11-Jan-17"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.75"
#define Module_HelpVersion "5.75 (17 Dec 2016)"
#define Module_LibraryVersionInfo "5:75"
#define Module_FullVersion "5.76"
#define Module_HelpVersion "5.76 (11 Jan 2017)"
#define Module_LibraryVersionInfo "5:76"
......@@ -3037,7 +3037,7 @@ LogOp_MapOut ROUT
MOV r6, r0, LSL #12
ARMop Cache_RangeThreshold,,,r12
CMP r6, r0
ORRHI r6, r6, #1
ORRLS r6, r6, #1
MOV r7, r3
LDR r12, [r12, #CamEntriesPointer]
......
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