diff --git a/VersionASM b/VersionASM
index 12366d42de76dc88f6349369e60273ab20b8783d..35355af4d58fd58755ddc7ad32d4492ab2723065 100644
--- a/VersionASM
+++ b/VersionASM
@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
-Module_MajorVersion SETS "4.85"
-Module_Version SETA 485
+Module_MajorVersion SETS "4.86"
+Module_Version SETA 486
Module_MinorVersion SETS ""
-Module_Date SETS "24 Aug 1999"
-Module_FullVersion SETS "4.85"
+Module_Date SETS "16 Sep 1999"
+Module_FullVersion SETS "4.86"
END
diff --git a/VersionNum b/VersionNum
index b134f877b8717e6e531f52e846791275e56cafb1..09ba937a481a09c7b7116b1c35f60a96ed6f5234 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,15 +1,15 @@
-/* (4.85)
+/* (4.86)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
-#define Module_MajorVersion_CMHG 4.85
+#define Module_MajorVersion_CMHG 4.86
#define Module_MinorVersion_CMHG
-#define Module_Date_CMHG 24 Aug 1999
+#define Module_Date_CMHG 16 Sep 1999
-#define Module_MajorVersion "4.85"
-#define Module_Version 485
+#define Module_MajorVersion "4.86"
+#define Module_Version 486
#define Module_MinorVersion ""
-#define Module_Date "24 Aug 1999"
+#define Module_Date "16 Sep 1999"
-#define Module_FullVersion "4.85"
+#define Module_FullVersion "4.86"
diff --git a/s/GetAll b/s/GetAll
index d9c1466bd7cfd3f315c4de0e0960f01b6e0cef5c..c8339022101ccddb7623f0390b5da5ac488f685a 100644
--- a/s/GetAll
+++ b/s/GetAll
@@ -482,9 +482,6 @@ InterlacedPointer SETL {TRUE} :LAND: STB ; enable code to do prop
GBLL ValidateCMOS ; Apply special CMOS-corruption detection code, and do minimal default settings.
ValidateCMOS SETL {TRUE} :LAND: STB
- GBLL UseHClk
-UseHClk SETL {TRUE} :LAND: STB ; Use HClk when driving TVs.
-
[ DebugHeaps
! 0, "*** WARNING *** Heap debugging assembled in"
]
diff --git a/s/NewReset b/s/NewReset
index e19aba23f748d0606fcbe2c47f48f9c715e0f150..28470c018cd9fd2c72473d2372ebcbfe9bd3486d 100644
--- a/s/NewReset
+++ b/s/NewReset
@@ -305,7 +305,7 @@ VIDCTAB
& &E0000401 ; CR: FIFO load 16 words, 1 bpp, ck/1, hclk
]
[ VIDCClockSource = "RCLK"
- & &E0000402 ; CR: FIFO load 16 words, 1 bpp, ck/1, rclk
+ & &E0000406 ; CR: FIFO load 16 words, 1 bpp, ck/2, rclk
]
; Don't bother programming all 256 palette entries, we'll be here all night
@@ -966,6 +966,8 @@ reset_loop
BHI cmos_reset
]
+ [ {FALSE}
+ ; Oh, just leave it be
MOV R0, #VduCMOS
BL Read
[ IOMD_C_MonitorType = 0 :LAND: MPEGPoduleNTSCNotPALMask = 0 :LAND: IOMD_C_PALNTSCType = 0
@@ -976,6 +978,7 @@ reset_loop
TEQ R0, #(Sync_Auto :OR: MonitorTypeAuto)
]
BNE cmos_reset
+ ]
; Year should be >=1995, <=2020
; (2020 is arbitrary, but everything breaks soon after that)
diff --git a/s/vdu/vdudecl b/s/vdu/vdudecl
index 9e2ffd8b3efcd58bb9098b2eba908ea1bab7e08d..e5a9a26ef45f36dbb457b19e8dd88bf3e5f9fe34 100644
--- a/s/vdu/vdudecl
+++ b/s/vdu/vdudecl
@@ -77,6 +77,7 @@ VIDCDataControl * &F0000000
; Pseudo-registers used to return additional information to kernel
+PseudoRegister_HClockSpeed * &FB000000 ; used to indicate VIDC hclock speed (and use it)
PseudoRegister_ClockSpeed * &FC000000 ; used to indicate real VIDC rclock speed
PseudoRegister_DPMSState * &FD000000 ; used to return desired DPMS state
[ ChrontelSupport
diff --git a/s/vdu/vdudriver b/s/vdu/vdudriver
index 842322b61b9c802d79b9e2479445442abdf1206b..75fd7fce536eae10bcb52a25a81fdda04b13d5bc 100644
--- a/s/vdu/vdudriver
+++ b/s/vdu/vdudriver
@@ -2104,7 +2104,7 @@ ProcessControlListItem ENTRY
& ProcessControlListDACControl ; 6 - DAC control
& ProcessControlListRGBPedestals ; 7 - RGB pedestal enables
& ProcessControlListExternalRegister ; 8 - External register
- & ProcessControlListNOP ; 9 - HClk select/specify
+ & ProcessControlListHClockSelect ; 9 - HClk select/specify
& ProcessControlListNOP ; 10 - RClk frequency
& ProcessControlListDPMSState ; 11 - DPMS state
@@ -2217,9 +2217,13 @@ ProcessControlListLCDOffsetRegister1
MOV r0, #LCDOffsetRegister1
B %BT20
+ProcessControlListHClockSelect
+ MOV r0, #PseudoRegister_HClockSpeed ; pseudo-register holding HClock speed
+ B %FT40
+
ProcessControlListDPMSState
MOV r0, #PseudoRegister_DPMSState ; pseudo-register holding DPMS state
- ORR r2, r2, r0 ; form combined value
+40 ORR r2, r2, r0 ; form combined value
STR r2, [r9, r0, LSR #22] ; store in register
EXIT
@@ -2230,6 +2234,7 @@ ProcessControlListDPMSState
;
; in: r0 = desired frequency (kHz)
; r1 = rclk frequency (kHz) (normally 24000)
+; r9 -> VIDC table
;
; out: r0 = bits to put in bits 0..15 of Frequency Synthesizer Register
; r1 = bits to put in bits 0..4 of Control Register
@@ -2252,28 +2257,17 @@ BestRangeError # 4
ComputeModuliStack * :INDEX: @
ComputeModuli ENTRY "r2-r12", ComputeModuliStack
- [ ChrontelSupport
- MOV r1, #CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift) ; use divide by 1
- LDR r0, =(63 :SHL: FSyn_RShift) :OR: (1 :SHL: FSyn_VShift) ; minimum V, maximum R
- EXIT
- |
- [ UseHClk :LAND: STB
-
-; TMD 09-Oct-96: Only check monitor lead type if there is the hardware, otherwise assume just TV
- [ IOMD_C_MonitorType <> 0
- BL TranslateMonitorLeadType ; -> r3=mode, r4=monitor, r5=sync
- CMP r4, #3
- BEQ %FT05
- ]
-
-; Use HClk
- LDR r1, =12500 ; if desired pixel clock
- CMP r0, r1
- MOVCC r1, #CR_HCLK :OR: ((2-1) :SHL: CR_PixelDivShift) ; if < 12.5MHz, use divide by 2
- MOVCS r1, #CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift) ; else use divide by 1
- LDR r0, =63 :OR: (1 :SHL: FSyn_VShift) ; minimum V, maximum R
- EXIT
- ]
+ LDR r1, [r9, #PseudoRegister_HClockSpeed:SHR:22] ; are we using HCLK?
+ CMP r1, #-1
+ BEQ %FT05 ; -1 => no, use VCLK/RCLK
+
+ BIC r1, r1, #&FF000000 ; r1 = HCLK frequency
+ SUB r1, r1, r1, LSR #2 ; r1 = HCLK * 3/4
+ CMP r0, r1
+ MOVLO r1, #CR_HCLK :OR: ((2-1) :SHL: CR_PixelDivShift) ; if < 3/4 HCLK, use divide by 2
+ MOVHS r1, #CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift) ; else use divide by 1
+ LDR r0, =(63 :SHL: FSyn_RShift) :OR: (1 :SHL: FSyn_VShift) ; minimum V, maximum R
+ EXIT
; Use VCLK/RCLK
05
@@ -2356,9 +2350,11 @@ ComputeModuli ENTRY "r2-r12", ComputeModuliStack
STR r8, BestVInOrOutOfRange
STR r14, BestRangeError
50
+ [ :LNOT: DontUseVCO ; If we don't use the VCO, R has to be 1
ADD r4, r4, #1
CMP r4, #16 ; R goes from 2 to 16 (was 2 to 64)
BLS %BT15
+ ]
ADD r3, r3, #1
CMP r3, #8 ; D goes from 1 to 8
@@ -2393,7 +2389,6 @@ ComputeModuli ENTRY "r2-r12", ComputeModuliStack
ORREQ r1, r1, #CR_RCLK ; if using VCO then set for VCLK, else RCLK
EXIT
- ] ; ChrontelSupport
] ; VIDCListType3
; *****************************************************************************