From af172483d3e6825afea74e7fa01cd694d75f9495 Mon Sep 17 00:00:00 2001
From: Jeffrey Lee <jlee@gitlab.riscosopen.org>
Date: Wed, 14 Sep 2011 23:41:21 +0000
Subject: [PATCH] Fix Cache_InvalidateAll_WB_CR7_Lx to do what it says on the
tin
Detail:
s/ARMops - My previous checkin mistakenly changed Cache_InvalidateAll_WB_CR7_Lx so that it cleans and invalidates the cache instead of just invalidating it. This fixes that.
Also fixed a warning caused by the trailing space going AWOL from the 'cache type register fields' comment.
Admin:
Tested on rev A2 BB-xM
Version 5.35, 4.79.2.98.2.52. Tagged as 'Kernel-5_35-4_79_2_98_2_52'
---
VersionASM | 10 +++++-----
VersionNum | 14 +++++++-------
s/ARMops | 4 ++--
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/VersionASM b/VersionASM
index bee0d80..3db775c 100644
--- a/VersionASM
+++ b/VersionASM
@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
-Module_MinorVersion SETS "4.79.2.98.2.51"
-Module_Date SETS "12 Sep 2011"
-Module_ApplicationDate SETS "12-Sep-11"
+Module_MinorVersion SETS "4.79.2.98.2.52"
+Module_Date SETS "15 Sep 2011"
+Module_ApplicationDate SETS "15-Sep-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
-Module_FullVersion SETS "5.35 (4.79.2.98.2.51)"
-Module_HelpVersion SETS "5.35 (12 Sep 2011) 4.79.2.98.2.51"
+Module_FullVersion SETS "5.35 (4.79.2.98.2.52)"
+Module_HelpVersion SETS "5.35 (15 Sep 2011) 4.79.2.98.2.52"
END
diff --git a/VersionNum b/VersionNum
index bd8426e..ae7167e 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
-#define Module_MinorVersion_CMHG 4.79.2.98.2.51
-#define Module_Date_CMHG 12 Sep 2011
+#define Module_MinorVersion_CMHG 4.79.2.98.2.52
+#define Module_Date_CMHG 15 Sep 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
-#define Module_MinorVersion "4.79.2.98.2.51"
-#define Module_Date "12 Sep 2011"
+#define Module_MinorVersion "4.79.2.98.2.52"
+#define Module_Date "15 Sep 2011"
-#define Module_ApplicationDate "12-Sep-11"
+#define Module_ApplicationDate "15-Sep-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
-#define Module_FullVersion "5.35 (4.79.2.98.2.51)"
-#define Module_HelpVersion "5.35 (12 Sep 2011) 4.79.2.98.2.51"
+#define Module_FullVersion "5.35 (4.79.2.98.2.52)"
+#define Module_HelpVersion "5.35 (15 Sep 2011) 4.79.2.98.2.52"
#define Module_LibraryVersionInfo "5:35"
diff --git a/s/ARMops b/s/ARMops
index 426a5de..0665d38 100644
--- a/s/ARMops
+++ b/s/ARMops
@@ -724,7 +724,7 @@ $var SETA $var+(CT_M_$sz:SHL:CT_M_pos)
; CPUDesc table for ARMv3-ARMv6
KnownCPUTable
-; /------Cache Type register fields-----\
+; /------Cache Type register fields-----\.
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
@@ -2001,7 +2001,7 @@ Cache_InvalidateAll_WB_CR7_Lx ROUT
; no clean, assume caller knows what's happening
;
Push "r1-r8,lr"
- MaintainDataCache_WB_CR7_Lx cleaninvalidate, loc
+ MaintainDataCache_WB_CR7_Lx invalidate, loc
MCR p15, 0, a1, c7, c5, 0 ; invalidate ICache
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB ,a1,,y ; Wait for cache/branch invalidation to complete
--
GitLab