diff --git a/VersionASM b/VersionASM
index 2d4a97c308bdf0058efa98534f1862ec126a88df..21ae89b4541fd04260af4e48db031cba7f45b994 100644
--- a/VersionASM
+++ b/VersionASM
@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
-Module_MinorVersion SETS "4.79.2.49"
-Module_Date SETS "16 Oct 2002"
-Module_ApplicationDate SETS "16-Oct-02"
+Module_MinorVersion SETS "4.79.2.50"
+Module_Date SETS "28 Oct 2002"
+Module_ApplicationDate SETS "28-Oct-02"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
-Module_FullVersion SETS "5.35 (4.79.2.49)"
-Module_HelpVersion SETS "5.35 (16 Oct 2002) 4.79.2.49"
+Module_FullVersion SETS "5.35 (4.79.2.50)"
+Module_HelpVersion SETS "5.35 (28 Oct 2002) 4.79.2.50"
END
diff --git a/VersionNum b/VersionNum
index d4904f6971c1c13665d848e8f830d34a9785d1f0..11023ed8a14591a7149e5d8fe5001ef2fdb231cf 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
-#define Module_MinorVersion_CMHG 4.79.2.49
-#define Module_Date_CMHG 16 Oct 2002
+#define Module_MinorVersion_CMHG 4.79.2.50
+#define Module_Date_CMHG 28 Oct 2002
#define Module_MajorVersion "5.35"
#define Module_Version 535
-#define Module_MinorVersion "4.79.2.49"
-#define Module_Date "16 Oct 2002"
+#define Module_MinorVersion "4.79.2.50"
+#define Module_Date "28 Oct 2002"
-#define Module_ApplicationDate "16-Oct-02"
+#define Module_ApplicationDate "28-Oct-02"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
-#define Module_FullVersion "5.35 (4.79.2.49)"
-#define Module_HelpVersion "5.35 (16 Oct 2002) 4.79.2.49"
+#define Module_FullVersion "5.35 (4.79.2.50)"
+#define Module_HelpVersion "5.35 (28 Oct 2002) 4.79.2.50"
#define Module_LibraryVersionInfo "5:35"
diff --git a/hdr/Copro15ops b/hdr/Copro15ops
index cf1e7b90b47ac2ae6d7186a47207da39e717e29f..d6c23652aa2ee33ffc01feba81a59bfcf48d6a53 100644
--- a/hdr/Copro15ops
+++ b/hdr/Copro15ops
@@ -98,18 +98,30 @@ C15 CN 15
MCR$cond ARM_config_cp,0,$reg,ARM_control_reg,C0,0
MEND
-;read MMU fault status
+;read MMU/external fault status
MACRO
ARM_read_FSR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,0
MEND
-;read MMU fault address
+;set MMU/external fault status
+ MACRO
+ ARM_write_FSR $reg,$cond
+ MCR$cond ARM_config_cp,0,$reg,ARM_FSR_reg,C0,0
+ MEND
+
+;read MMU/external fault address
MACRO
ARM_read_FAR $reg,$cond
MRC$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,0
MEND
+; set MMU/external fault address
+ MACRO
+ ARM_write_FAR $reg,$cond
+ MCR$cond ARM_config_cp,0,$reg,ARM_FAR_reg,C0,0
+ MEND
+
;read ID register to register $id
;bits 15:12 of returned ID will be 0,7,8,10 for ARM 6,7,8,A
MACRO
diff --git a/s/AMBControl/memmap b/s/AMBControl/memmap
index 2fc370b2a3a157255fa67df0832c3d445c1bc887..ec7ef5845cc0c836e6bb30dcff5946ffd7469655 100644
--- a/s/AMBControl/memmap
+++ b/s/AMBControl/memmap
@@ -56,7 +56,10 @@
;
; entry: r0 = aborting address (data address for data abort, instruction address
; for prefetch abort), r1-r7 trashable, no stack
+; r1 = 1 for prefetch abort, 0 for data abort
+; FSR valid for data aborts, unpredictable for prefetch aborts
; exit: r0 = non-zero (NE status) if abort was expected and fixed up, zero (EQ status) if not
+; FAR,FSR,SPSR_abt,lr_abt preserved
;
AMB_LazyFixUp ROUT
MOV r7,r12
@@ -64,13 +67,18 @@ AMB_LazyFixUp ROUT
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;not initialised!
- LDR r1,AMBFlags
- TST r1,#AMBFlag_LazyMapIn_disable :OR: AMBFlag_LazyMapIn_suspend
+ LDR r2,AMBFlags
+ TST r2,#AMBFlag_LazyMapIn_disable :OR: AMBFlag_LazyMapIn_suspend
BNE %FT90 ;not active
- LDR r1,AMBMappedInNode
- CMP r1,#0
+ LDR r2,AMBMappedInNode
+ CMP r2,#0
BEQ %FT90 ;no current node
- LDR r2,[r1,#AMBNode_Npages]
+ ARM_read_FSR r6 ;hang onto FSR in case we have to preserve it
+ TEQ r1,#1 ;if data abort
+ ANDNE r3,r6,#&F
+ TEQNE r3,#7 ; and not a page translation fault
+ BNE %FT20 ; then not a lazy abort (and FAR may be invalid anyway)
+ LDR r2,[r2,#AMBNode_Npages]
SUBS r0,r0,#ApplicationStart
BMI %FT20 ;abort not in current app space
MOV r0,r0,LSR #Log2PageSize ;address now in terms of pages from ApplicationStart
@@ -132,6 +140,8 @@ AMB_LazyFixUp ROUT
BEQ %FT90
MRS r0,SPSR ;preserve SPSR_abort for original abort details
MOV r4,lr ;preserve lr_abort so we can return properly (!)
+ ARM_read_FAR r5 ;preserve FAR in case client abort handler wants to read it
+ ;preserve FSR (already in r6) similarly
30
LDR r3,[r1] ;bring that page in by the magic of aborts
SUBS r2,r2,#1
@@ -139,6 +149,8 @@ AMB_LazyFixUp ROUT
BNE %BT30
MSR SPSR_cxsf,r0 ;SPSR for original abort
MOV lr,r4 ;restore return address
+ ARM_write_FAR r5 ;restore FAR
+ ARM_write_FSR r6 ;restore FSR
;
90
MOVS r0,#0
diff --git a/s/ARM600 b/s/ARM600
index 7a265070ae2e993f9be665140b2911921b780e7e..11f88286c6889920f46bc24ad2657f5407fe39ea 100644
--- a/s/ARM600
+++ b/s/ARM600
@@ -2458,6 +2458,7 @@ UndPreVeneer ROUT
PAbPreVeneer ROUT
Push "r0-r7, lr" ; wahey, we have an abort stack
SUB r0, lr_abort, #4 ; aborting address
+ MOV r1,#1
BL AMB_LazyFixUp ; can trash r0-r7, returns NE status if claimed and fixed up
Pull "r0-r7, lr", NE ; restore regs and
SUBNES pc, lr_abort, #4 ; restart aborting instruction if fixed up
@@ -2524,17 +2525,13 @@ DAbPreVeneer ROUT
STR lr_abort, [r13_abort, #15*4] ; save old PC, ie instruction address
[ ChocolateAMB
- ARM_read_FSR r0
- AND r0, r0, #&F
- TEQ r0, #7
- BNE DAb_NotTranslationFault
ARM_read_FAR r0 ; aborting address
+ MOV r1,#0
BL AMB_LazyFixUp ; can trash r0-r7, returns NE status if claimed and fixed up
LDR lr_abort, [r13_abort, #15*4] ; restore lr_abort
LDMIA r13_abort, {r0-r7} ; restore regs
ADDNE r13_abort, r13_abort, #17*4 ; if fixed up, restore r13_abort
SUBNES pc, lr_abort, #8 ; and restart aborting instruction
-DAb_NotTranslationFault
]
MRS r0, SPSR ; r0 = PSR when we aborted