Commit 521ac671 authored by Jeffrey Lee's avatar Jeffrey Lee

Merge in latest changes from main branch

Version 5.97, 4.129.2.7. Tagged as 'Kernel-5_97-4_129_2_7'
parents 2cc5ebc7 5bc10832
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.89"
Module_Version SETA 589
Module_MinorVersion SETS "4.129.2.6"
Module_Date SETS "10 Sep 2017"
Module_ApplicationDate SETS "10-Sep-17"
Module_MajorVersion SETS "5.97"
Module_Version SETA 597
Module_MinorVersion SETS "4.129.2.7"
Module_Date SETS "16 Feb 2018"
Module_ApplicationDate SETS "16-Feb-18"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.89 (4.129.2.6)"
Module_HelpVersion SETS "5.89 (10 Sep 2017) 4.129.2.6"
Module_FullVersion SETS "5.97 (4.129.2.7)"
Module_HelpVersion SETS "5.97 (16 Feb 2018) 4.129.2.7"
END
/* (5.89)
/* (5.97)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 5.89
#define Module_MinorVersion_CMHG 4.129.2.6
#define Module_Date_CMHG 10 Sep 2017
#define Module_MajorVersion_CMHG 5.97
#define Module_MinorVersion_CMHG 4.129.2.7
#define Module_Date_CMHG 16 Feb 2018
#define Module_MajorVersion "5.89"
#define Module_Version 589
#define Module_MinorVersion "4.129.2.6"
#define Module_Date "10 Sep 2017"
#define Module_MajorVersion "5.97"
#define Module_Version 597
#define Module_MinorVersion "4.129.2.7"
#define Module_Date "16 Feb 2018"
#define Module_ApplicationDate "10-Sep-17"
#define Module_ApplicationDate "16-Feb-18"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.89 (4.129.2.6)"
#define Module_HelpVersion "5.89 (10 Sep 2017) 4.129.2.6"
#define Module_LibraryVersionInfo "5:89"
#define Module_FullVersion "5.97 (4.129.2.7)"
#define Module_HelpVersion "5.97 (16 Feb 2018) 4.129.2.7"
#define Module_LibraryVersionInfo "5:97"
......@@ -1235,6 +1235,11 @@ DebuggerSpace_Size * ?DebuggerSpace
|
DebuggerSpace * &2000 ; Debugger gets a page all to itself!
DebuggerSpace_Size * &1000
[ CompatibilityPage
CompatibilityPageEnabled # 1 ; 0 or 1 as appropriate
]
AlignSpace
]
IICBus_Count * 5 ; 5 buses is enough for all current machines
......
......@@ -60,9 +60,6 @@ ValidateCMOS SETL {TRUE} ; and do minimal default setting
GBLL ChecksumCMOS ; Inspect the CMOS checksum byte, and act like a CMOS reset if it's
ChecksumCMOS SETL {TRUE} ; invalid. Also, calculate CMOS checksum and write it when needed.
GBLL IgnoreVRAM ; if true, don't add VRAM to the RAM list (+ don't use for screen)
IgnoreVRAM SETL {FALSE}
GBLL ShrinkableDAs ; if true, support Shrinkable Dynamic Areas (eg. CacheFS)
ShrinkableDAs SETL {TRUE}
......@@ -72,18 +69,16 @@ DA_Batman SETL {TRUE} ; concept of sparsely mapped dyn
LongCLISize * 1024 ; buffer size for long commands
GBLL SASTMhatbroken ; whether ROM must support SA110's with broken STM^ (revision 3 should fix this)
GBLL ARM6support
GBLL XScaleMiniCache ; is the XScale mini data-cache used (at all)
GBLL XScaleJTAGDebug
SASTMhatbroken SETL SupportARMv4 :LAND: NoARMv5
SASTMhatbroken SETL SupportARMv4 :LAND: NoARMv5
GBLL CacheCleanerHack ; Cache clean hack in ClearPhysRAM for platforms that use DCacheCleanAddress. Does not work with all CPUs!
GBLL InterruptDelay ; True if we might be running on a CPU with CPUFlag_InterruptDelay set (e.g. StrongARM)
CacheCleanerHack SETL {TRUE}
InterruptDelay SETL SupportARMv4 :LAND: NoARMv5
GBLL ARM6support
GBLL XScaleMiniCache ; is the XScale mini data-cache used (at all)
GBLL XScaleJTAGDebug
ARM6support SETL (MEMM_Type = "ARM600") :LAND: NoARMv4
XScaleMiniCache SETL {FALSE}
XScaleJTAGDebug SETL {TRUE}
......@@ -183,13 +178,7 @@ PMPParanoid SETL {FALSE} ; Validate PMPs after most ops
GBLL PMPRAMFS
PMPRAMFS SETL {TRUE} ; Whether RAMFS DA is a PMP (requires compatible RAMFS module)
[ PMPRAMFS
PMPRAMFS_Size * 256 ; Number of logical pages (physical size is unlimited)
|
GBLA MaxRAMFS_Size
MaxRAMFS_Size SETA 128 ; Max size available for RAM Disc
]
GBLL CacheablePageTables
CacheablePageTables SETL {TRUE} ; Use cacheable page tables where possible
......
......@@ -1065,7 +1065,7 @@ KnownCPUFlags
DCD 0, 0 ; Cortex_A8
DCD 0, 0 ; Cortex_A9
DCD 0, 0 ; Cortex_A12
DCD 0, 0 ; Cortex_A15
DCD CPUFlag_NoDCacheDisable, 0 ; Cortex_A15
DCD 0, 0 ; Cortex_A17
DCD CPUFlag_NoDCacheDisable, 0 ; Cortex_A53
DCD 0, 0 ; Cortex_A57
......
......@@ -2528,23 +2528,4 @@ Read_Configd_Sync Entry
BL ReadMultiField
EXIT
SetUpPrinterBuffer Entry "r1-r3"
MOV r0, #PrinterBufferCMOS
BL Read
LDR r2, =ZeroPage
LDR r2, [r2, #Page_Size]
MULS r3, r2, r0
BEQ %FT10 ; if zero, then use default area & size
BL ClaimSysHeapNode ; else claim space from system heap
BVC %FT20 ; if no error then OK, else use default
10
LDR r2, =PrintBuff ; use default buffer
MOV r3, #PrintBuffSize
20
LDR r0, =ZeroPage
STR r2, [r0, #PrinterBufferAddr]
STR r3, [r0, #PrinterBufferSize]
EXIT
END
......@@ -1184,8 +1184,8 @@ MAI_CompatibilityPage
[ CompatibilityPage
MOV r1, #0
MOV r2, #4096
LDR r0, =L2PT
LDR r3, [r0]
LDR r0, =ZeroPage
LDRB r3, [r0,#CompatibilityPageEnabled]
CMP r3, #0
MOVNE r3, #4096
]
......@@ -1717,15 +1717,20 @@ ChangeCompatibility ROUT
MOV pc, lr
|
Entry "r0-r11", DANode_NodeSize
; Peek L2PT to see if anything's mapped to &0
LDR r8, =L2PT
LDR r0, [r8]
CMP r0, #0
MOVNE r0, #1
FRAMSTR r0,,r1 ; return pre-change state in r1
LDR r12, =ZeroPage
LDRB r0, [r12, #CompatibilityPageEnabled]
FRAMSTR r0,,r1 ; return pre-change state in r1 (will be updated later, as necessary)
CMP r1, #-1
CMPNE r0, r1
EXIT EQ
; If we're attempting to enable it, make sure nothing else has mapped itself in to page zero
LDR r8, =L2PT
CMP r1, #0
LDRNE r0, [r8]
CMPNE r0, #0
MOVNE r1, #-1
FRAMSTR r1,NE
EXIT NE
; Set up temp DANode on the stack so we can use a Batcall to manage the mapping
MOV r2, sp
MOV r0, #DynAreaFlags_NotCacheable
......@@ -1747,6 +1752,7 @@ ChangeCompatibility ROUT
; If we just enabled the page, fill it with the special value and then change it to read-only
FRAMLDR r1
RSBS r1, r1, #1 ; invert returned state, to be correct for the above action
STRB r1, [r12, #CompatibilityPageEnabled] ; Also update our state flag
FRAMSTR r1
EXIT EQ
MOV r0, #0
......@@ -1757,7 +1763,6 @@ ChangeCompatibility ROUT
STR r2, [r0], #4
CMP r0, #4096
BNE %BT10
LDR r12, =ZeroPage
LDR r7, [r12, #MaxCamEntry]
MOV r4, #0
BL logical_to_physical
......@@ -1858,8 +1863,8 @@ CheckMemoryAccess ROUT
|
[ CompatibilityPage
; Zero page compatibility page
LDR r3, =L2PT
LDR r3, [r3]
LDR r3, =ZeroPage
LDRB r3, [r3, #CompatibilityPageEnabled]
CMP r3, #0
BEQ %FT05
MOV r3, #0
......
......@@ -220,10 +220,12 @@ ModuleInit Entry "r0-r12"
ADRL r6, SysModules_Info+4
SUB sp, sp, #4 ; anchor new list on stack for now
MOV r9, sp ; pointer to 'previous' node
LDR r9, =ZeroPage+ROMModuleChain ; pointer to 'previous' node
LDR r12, [r9]
Push "r12" ; keep keyboard scan chain anchor
MOV r8, #0 ; initial head ptr is zero
STR r8, [r9] ; set up null list
MOV r3, #-1 ; podule -1 is main ROM
MOV r10, #0 ; chunk number 0 to start
10
......@@ -252,8 +254,7 @@ ModuleInit Entry "r0-r12"
BL AddROMModuleNode
BVS %FT50 ; if failed then can't add any more ROMs!
LDR r12, =ZeroPage+ROMModuleChain
LDR r12, [r12] ; keyboard scan chain may have seen this module
LDR r12, [sp, #0*4] ; keyboard scan chain may have seen this module
12
TEQ r12, #0
BEQ %FT18
......@@ -324,7 +325,6 @@ ModuleInit Entry "r0-r12"
STRB r1, [r2], #1
TEQ r1, #0
BNE %BT24
MOV r14, #(1 :SHL: 16) ; bit mask ready to shift
CMP r3, #-1
BLT %FT30
......@@ -373,17 +373,14 @@ ModuleInit Entry "r0-r12"
50
; during keyboard scan some ROM (only) modules were already started, switch chains
; free the keyboard scan chain as it's redundant now
LDR r12, =ZeroPage+ROMModuleChain
Pull "r2"
LDR r9, [r12] ; old anchor
STR r2, [r12]
Pull "r9" ; recover keyboard scan chain anchor
51
TEQ r9, #0
BEQ %FT58
MOV r2, r9 ; now free the keyboard scan chain
MOV r2, r9
LDR r9, [r9, #ROMModule_Link]
[ ChocolateSysHeap
ASSERT ChocolateMRBlocks = ChocolateBlockArrays + 12
......
......@@ -211,8 +211,11 @@ DatCopy
LDR r0, =ZeroPage
STR r2, [r0, #ResetIndirection]
MOV r3, #0 ; initialise abort list
MOV r3, #0 ; zero-initialise abort list, and other key workspace
STR r3, [r0, #AbortIndirection]
[ CompatibilityPage
STRB r3, [r0, #CompatibilityPageEnabled]
]
; Now the SWI despatch + low part of SWI table
ADRL R3, DirtyBranch
......@@ -268,13 +271,12 @@ conversionSWIfill
LDR R1, =DuffEntry ; nothing will be here!!
STR R1, [R0, #Curr_Active_Object]
; let's boogie with the CMOS for a bit
; read info and move as much memory as we can
; Get creating the essential areas
DebugTX "InitDynamicAreas"
BL InitDynamicAreas
; RMA
; RMA
Push "r0-r12"
MOV r1, #ChangeDyn_RMA ; Area number
MOV r2, #4096 ; Initial size
......@@ -288,7 +290,7 @@ conversionSWIfill
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
Pull "r0-r12"
; Screen
; Screen
Push "r0-r12"
MOV r0, #ScreenSizeCMOS
BL Read
......@@ -299,7 +301,8 @@ conversionSWIfill
LDR r5, [r5, #VideoSizeFlags] ; maximum size
MOV r5, r5, LSR #12
MOV r5, r5, LSL #12
BL MassageScreenSize
BL MassageScreenSize ; Clamps the initial size regardless of the
; contents of the ScreenSizeCMOS
MOV r1, #ChangeDyn_Screen ; area number
MOV r2, r0 ; initial size
......@@ -315,84 +318,9 @@ conversionSWIfill
STR r3, [r7, #ScreenEndAddr]
Pull "r0-r12"
; SpriteArea
Push "r0-r12"
MOV r0, #0 ; initialise SpriteSize to zero
[ ZeroPage = 0
STR r0, [r0, #SpriteSize] ; (fixes bug MED-00811)
|
LDR r1, =ZeroPage
STR r0, [r1, #SpriteSize] ; (fixes bug MED-00811)
]
MOV r0, #SpriteSizeCMOS ; find out how much spritesize configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r1, #ChangeDyn_SpriteArea ; Area number
MOV r3, #-1 ; Base address dynamic
MOV r4, #AreaFlags_Sprites ; Area flags
MOV r5, #16*1024*1024 ; Maximum size (changed from -1, address space preservation)
ADRL r6, DynAreaHandler_Sprites ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_SpriteArea ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
Pull "r0-r12"
; RAMDisc
Push "r0-r12"
MOV r1, #ChangeDyn_RamFS ; Area number
MOV r3, #-1 ; Base address dynamic
ARM_read_ID r4
AND r4, r4, #&F000
CMP r4, #&A000
MOVEQ r4, #AreaFlags_RAMDisc_SA ; Area flags, if StrongARM (introduced for Ursula)
MOVNE r4, #AreaFlags_RAMDisc ; Area flags
[ PMPRAMFS
MOV r5, #PMPRAMFS_Size*4096
ORR r4, r4, #DynAreaFlags_PMP
MOV r2, #0
ORR r4, r4, #DynAreaFlags_NeedsSpecificPages
MOV r9, #0
|
MOV r0, #RAMDiscCMOS ; find out how much RAM disc configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r5, #MaxRAMFS_Size*1024*1024 ; A trade off between nice big disc and complete waste of address space
]
ADRL r6, DynAreaHandler_RAMDisc ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_RAMDisc ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
[ PMPRAMFS
; Currently, physical memory pools must be created with 0 size, then resized afterwards
MOV r0, #RAMDiscCMOS ; find out how much RAM disc configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOVS r1, r2
MOV r0, #ChangeDyn_RamFS
SWINE XOS_ChangeDynamicArea
]
Pull "r0-r12"
; FontArea
Push "r0-r12"
MOV r0, #FontCMOS ; find out how much font cache configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r1, #ChangeDyn_FontArea ; Area number
MOV r3, #-1 ; Base address dynamic
MOV r4, #AreaFlags_FontArea ; Area flags
MOV r5, #32*1024*1024 ; Maximum size changed from -1 for Ursula (limit address
; space usage on large memory machines)
ADRL r6, DynAreaHandler_FontArea ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_FontArea ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
Pull "r0-r12"
LDR R0, =(512*1024):SHR:12 ; 512k of RAM in aplspace should be plenty for ROM init. Theoretically we don't need any at all, but having some there should make it easier to debug any ROM init failures.
LDR R0, =(512*1024):SHR:12 ; 512k of RAM in aplspace should be plenty for ROM init.
; Theoretically we don't need any at all, but having some there
; should make it easier to debug any ROM init failures.
MOV R3, #AppSpaceStart ; aplwork start
LDR R1, =ZeroPage+AplWorkSize ; aplwork size
MOV r11, #AreaFlags_AppSpace
......@@ -497,8 +425,6 @@ clearmswis
BL ExecuteInit
DebugTX "KeyInit"
BL KeyInit
DebugTX "MouseInit"
BL MouseInit
DebugTX "OscliInit"
BL OscliInit ; before initialising modules
......@@ -599,7 +525,6 @@ clearmswis
; everything from InitDynamicAreas
; RMA => not cleared, it's in use
; Screen => not cleared, the next CLS will do that
; SpriteArea, RAMDisc, FontArea => not cleared, clients write their own data structures
; and
; Application space (from FudgeSomeAppSpace) => cleared unconditionally
; Free pool => clear now if HAL didn't
......@@ -644,6 +569,7 @@ cmos_checks
LDR R1, [R0]
TST R1, #OSStartFlag_NoCMOS ; If no CMOS, reset for sensible cache
BNE cmos_reset
TST R1, #OSStartFlag_POR
BEQ no_cmos_reset ; not a power on reset
DebugTX "POR detected"
......@@ -717,6 +643,16 @@ no_cmos_reset
init_other_modules
; init that's deferrable until the CMOS is sanitised
DebugTX "ReadDefaults"
BYTEWS WsPtr
BL ReadHardCMOSDefaults
BL ReadCMOSDefaults
DebugTX "InitHostedDAs"
BL InitHostedDAs
DebugTX "MouseInit"
BL MouseInit
; now go back and load the other modules, scan podules, accounting for frugal bits
DebugTX "ModuleInit"
BL ModuleInit
......@@ -742,6 +678,16 @@ init_other_modules
MOV R0, #FSControl_SelectFS ; set configured filing system
SWI XOS_FSControl
; Update territory in case it changed after ModuleInitForKbdScan
MOV R0, #ReadCMOS
MOV R1, #TerritoryCMOS
SWI XOS_Byte
EOR R0, R2, #1 ; encoded so that 0 => TerritoryNum_UK
SWI XTerritory_Select
; Update RTC now all the modules are running
SWI XOS_ResyncTime
[ DebugROMInit
SWI XOS_WriteS
= "Service_PostInit",0
......@@ -771,9 +717,6 @@ init_other_modules
STRVCB lr, [lr, #ErrorSemaphore] ; then allow errors to be translated
]
; Update RTC now all the modules are running
SWI XOS_ResyncTime
; OS_ReadSysInfo 9,2 now relies on the Territory module, which may
; enable IRQs. But the PRMs say OS_ReadSysInfo shouldn't alter the IRQ
; state. So call it once here just to initialise the string which it
......
......@@ -1326,45 +1326,40 @@ OscliTidy ROUT ; shut down redirection, restore permanent FS
RemoveOscliCharJobs ROUT
Push "R0-R2, lr"
LDR R0, =ZeroPage
LDRB R1, [R0, #RedirectInHandle]
CMP R1, #0
ASSERT (ZeroPage :AND: 255) = 0
STRNEB R0, [R0, #RedirectInHandle]
; Release WrchV before attempting to close the file handles. This protects
; against output going missing if it happens during the close operation(s)
; E.g. if we're running in a task window and the output device uses
; OS_UpCall 6, our WrchV hook may be left installed when control is
; returned to the Wimp: https://www.riscosopen.org/tracker/tickets/420
MOV R2, #0
MOV R0, #WrchV
ADR R1, RedirectWrch
SWI XOS_Release
[ ZeroPage <> 0
MOV R0, #0
LDR R2, =ZeroPage
]
LDRB R1, [R2, #RedirectInHandle]
CMP R1, #0
MOVNE R0, #0
STRNEB R0, [R2, #RedirectInHandle]
SWINE XOS_Find
LDR R0, =ZeroPage ; May have got error (discarded)
LDRB R1, [R0, #RedirectOutHandle]
LDRB R1, [R2, #RedirectOutHandle]
CMP R1, #0
ASSERT (ZeroPage :AND: 255) = 0
STRNEB R0, [R0, #RedirectOutHandle]
[ ZeroPage <> 0
MOV R0, #0 ; May have got error (discarded)
]
MOVNE R0, #0 ; May have got error (discarded)
STRNEB R0, [R2, #RedirectOutHandle]
SWINE XOS_Find
MOV R2, #0
MOV R0, #WrchV
ADR R1, RedirectWrch
SWI XOS_Release
CLRV
Pull "R0-R2, PC"
RedirectWrch ROUT
Push "R1, R2"
SavePSR R2
Push "R1"
LDR R1, =ZeroPage
LDRB R1, [R1, #RedirectOutHandle]
SWI XOS_BPut
RestPSR R2 ; VClear in entry psr
Pull "R1, R2, pc", VC
RedirectError
Pull "R1, pc", VC
BL RemoveOscliCharJobs
ORR R2, R2, #V_bit
RestPSR R2
Pull "R1, R2, pc"
SETV
Pull "R1, pc"
; **************************************************************************
;
......
......@@ -99,10 +99,6 @@ KeyPostInit ROUT
Pull R14 ; restore I_bit indication
PLP ; set I_bit from this
LDROSB R1, LastBREAK ; is it a soft reset ?
TEQ R1, #SoftReset
Pull PC, EQ ; if so, then exit
MOV R0, #OsByte_Country
LDROSB R1, Country
SWI XOS_Byte
......
......@@ -25,7 +25,9 @@ ExecuteInit ROUT
BYTEWS WsPtr
LDRB R1, LastBREAK ; 0 => soft, 1 => power-on, 2 => hard
CMP R1, #1
CMP R1, #PowerOnReset
ASSERT SoftReset < PowerOnReset
ASSERT PowerOnReset < ControlReset
ADRCC R2, SoftResetVars
ADREQ R2, PowerOnResetVars
ADRHI R2, HardResetVars
......@@ -38,6 +40,11 @@ ExecuteInit ROUT
STRCS R3, TimerBeta +4
MOV R4, R1 ; preserve LastBREAK
MOV R1, #32 ; default FX11 and FX12
STRB R1, KeyRepDelay
MOV R1, #8
STRB R1, KeyRepRate
MOV R1, WsPtr ; start at the beginning
ADR R11, ByteVarInitTable
......@@ -66,6 +73,11 @@ BuffPtrInitLoop
STR R1, PrinterActive ; (R1=0)
; initialise SpriteSize to zero (fixes bug MED-00811)
LDR R2, =ZeroPage
STR R1, [R2, #SpriteSize]
; Initialise event semaphores
ADR R0, EventSemaphores
......@@ -85,15 +97,11 @@ BuffPtrInitLoop
MOV R0, #0 ; EOR with 0
BL UpdateLatchB
LDRB R0, LastBREAK
TEQ R0, #0
BEQ %FT20
LDR R1, =ZeroPage
MOV R0, #4_3330 ; Assume VGA during osinit
STRB R0, [R1, #MonitorLeadType]
BL ReadMachineType
BL ReadUniqueID
BL ReadHardCMOSDefaults
20
BL ReadCMOSDefaults
Push "r9,r12"
AddressHAL
......@@ -119,10 +127,82 @@ secs0070 * (86400*(365*70+18)) ; from time() in risc_oslib.c.armsys
LTORG
; *****************************************************************************
;
; InitHostedDAs - Set up the dynamic areas that we kindly host on
; behalf of other parts of the OS (SpriteUtils, RamFS, Font Manager)
InitHostedDAs
Push "r0-r12, lr"
; SpriteArea
MOV r0, #SpriteSizeCMOS ; find out how much spritesize configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r1, #ChangeDyn_SpriteArea ; Area number
MOV r3, #-1 ; Base address dynamic
MOV r4, #AreaFlags_Sprites ; Area flags
MOV r5, #16*1024*1024 ; Maximum size (changed from -1, address space preservation)
ADRL r6, DynAreaHandler_Sprites ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_SpriteArea ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
; RAMDisc
MOV r1, #ChangeDyn_RamFS ; Area number
MOV r3, #-1 ; Base address dynamic
ARM_read_ID r4
AND r4, r4, #&F000
CMP r4, #&A000
MOVEQ r4, #AreaFlags_RAMDisc_SA ; Area flags, if StrongARM (introduced for Ursula)
MOVNE r4, #AreaFlags_RAMDisc ; Area flags
[ PMPRAMFS
MOV r5, #PMPRAMFS_Size*4096
ORR r4, r4, #DynAreaFlags_PMP
MOV r2, #0
ORR r4, r4, #DynAreaFlags_NeedsSpecificPages
MOV r9, #0
|
MOV r0, #RAMDiscCMOS ; find out how much RAM disc configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r5, #128*1024*1024 ; A trade off between nice big disc and complete waste of address space
]
ADRL r6, DynAreaHandler_RAMDisc ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_RAMDisc ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
[ PMPRAMFS
; Currently, physical memory pools must be created with 0 size, then resized afterwards
MOV r0, #RAMDiscCMOS ; find out how much RAM disc configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOVS r1, r2
MOV r0, #ChangeDyn_RamFS
SWINE XOS_ChangeDynamicArea
]
; FontArea
MOV r0, #FontCMOS ; find out how much font cache configured
BL GetConfiguredSize ; in: r0 = CMOS address, out: r2 = size
MOV r1, #ChangeDyn_FontArea ; Area number
MOV r3, #-1 ; Base address dynamic
MOV r4, #AreaFlags_FontArea ; Area flags
MOV r5, #32*1024*1024 ; Maximum size changed from -1 for Ursula (limit address
; space usage on large memory machines)
ADRL r6, DynAreaHandler_FontArea ; Pointer to handler
MOV r7, #-1 ; Use base address as workspace ptr
ADRL r8, AreaName_FontArea ; Title string - node will have to be reallocated
; after module init, to internationalise it
BL DynArea_Create ; ignore any error, we're stuffed if we get one!
Pull "r0-r12, pc"
; *****************************************************************************
;
; ReadHardCMOSDefaults - Read CMOS values for a hard/power-on reset
; NB must be called in supervisor mode
; On entry WsPtr -> BYTEWS
ReadHardCMOSDefaults
Push R14
......@@ -173,7 +253,7 @@ ReadHardCMOSDefaults
; *****************************************************************************
;
; ReadCMOSDefaults - Read CMOS values for any reset
; NB must be called in supervisor mode
; On entry WsPtr -> BYTEWS
ReadCMOSDefaults
Push R14
......@@ -235,7 +315,7 @@ PostInit ROUT
Push R14
BYTEWS WsPtr
LDRB R0, LastBREAK ; get reset type
TEQ R0, #0
TEQ R0, #SoftReset
BEQ %FT10 ; [soft reset, skip]
SWI XPortable_ReadFeatures
......@@ -253,6 +333,29 @@ PostInit ROUT
10
Pull PC
; *****************************************************************************
;
; SetUpPrinterBuffer - create the printer buffer
SetUpPrinterBuffer Entry "r1-r3"
MOV r0, #PrinterBufferCMOS
BL Read
LDR r2, =ZeroPage
LDR r2, [r2, #Page_Size]
MULS r3, r2, r0
BEQ %FT10 ; if zero, then use default area & size
BL ClaimSysHeapNode ; else claim space from system heap
BVC %FT20 ; if no error then OK, else use default
10
LDR r2, =PrintBuff ; use default buffer
MOV r3, #PrintBuffSize
20
LDR r0, =ZeroPage
STR r2, [r0, #PrinterBufferAddr]
STR r3, [r0, #PrinterBufferSize]
EXIT
; *****************************************************************************
;
; UpdateLatchB - update latch B and soft copy
......@@ -407,18 +510,6 @@ ByteVarInitTableSize * ByteVarInitTableEnd - ByteVarInitTable
oldirqowner & IRQ
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; ReadMachineType - Determine machine type and store it in IOSystemType
;
ReadMachineType Entry "r0-r12"
LDR r1, =ZeroPage
MOV r0, #4_3330 ; Assume VGA during osinit
STRB r0, [r1, #MonitorLeadType]