• Jeffrey Lee's avatar
    Prevent disabling of the D-cache on Cortex-A53. Other OS_MMUControl 0 fixes. · d7299988
    Jeffrey Lee authored
    Detail:
      On Cortex-A53, a load/store exclusive instruction will abort if it targets non-cacheable memory or if the D-cache is disabled. Since the correct operation of these instructions is important to the OS and apps, it makes sense to prevent *Cache Off / OS_MMUControl 0 from being able to disable the D-cache on such systems.
      hdr/OSMisc, s/ARMops - Add new OS_PlatformFeatures 0 flag to indicate when disabling of the D-cache isn't allowed
      s/VMSAv6 - Update MMUControl_ModifyControl to force the D-cache to always be on when the "unsafe to disable D-cache" PlatformFeatures flag is set. Also, disallow mismatched I+D cache settings if we have an L2 cache (causes issues due to IMB ops only flushing to PoU), and fix dangerous D-cache invalidation when it's only the I-cache which is being disabled
      s/ARM600 - Clean up MMUControl_ModifyControl a bit so that it's a closer match to the VMSAv6 version, and fix the dangerous D-cache invalidation.
    Admin:
      Tested on ARM11, Cortex-A7, Cortex-A53
    
    
    Version 5.62. Tagged as 'Kernel-5_62'
    d7299988
OSMisc 7.99 KB