GitLab

Basic HAL device to expose the GENET peripheral for the driver.

* Requires 'enable_gic=1' in config.txt (or Pi4 dtb to be present?)
* IRQs are managed via the GIC, FIQs via the BCM2838 FIQ controller
* Implemented in s.IntVC6 to avoid making s.Interrupts too
confusing.
* Previous VC6 interrupt support removed from s.Interrupts
* From the OS's perspective, interrupt numbers mostly remain
unchanged. However iDev_QA7 interrupts are unavailable, and some of
the BCM2838 interrupts have been overlaid ontop of them.
* Device drivers must take care to issue HAL_IRQClear, as that is
a new requirement for this HAL

RAM sizes above 1GB are not reported by the usual mailbox property, and it
seems unlikely that this will change because the VC RAM allocation has to
remain within the bottom 1GB of the address space (the VC still uses the
upper two bits of its addresses for cache policy) and this property cannot
describe a non-contiguous range. Use the board revision bitfield to recognise
when additional general-purpose RAM exists above the VC allocation. For now,
we're running in "low peripherals" mode, so the top 64MB of 4GB RAM machines
is inaccessible. If the VC allocation is also 64MB, that means the startup
banner of Pi 4 will read 960MB, 1984MB or 3968MB.

Also fix HAL_PhysInfo (and by implication, OS_Memory 6 and 7) to report the
full 35-bit physical address space on Pi 4. The `range` struct filled in by
HAL_PhysInfo has not been extended to 64-bit physical addresses because it
describes RAM, and for now at least, RAM just squeezes into 32-bit addresses.

This controller is now preferred over the legacy EMMC controller, and it is
capable of UHS speeds (pending support in SDIODriver).

Requires RiscOS/Sources/HWSupport/SD/SDIODriver!4

Both still use GIC bypass mode. Assuming for now that extended GPU peripherals
can't support FIQ without GIC (it seems as though they either all use IRQ or
all use FIQ, and RISC OS isn't set up for there being multiple FIQ sources
active at once).

Because the mini-UART clock is derived from the core clock, and this varies
by hardware platform and even firmware version, move the initial mailbox
read to before UART initialisation so that this information is available.

Also:
* the IO region previously used only for the QA7 extensions now holds a GIC
  as well on Pi 4, so give it a more generic name
* there's a new, second peripheral IO region to map in as well

Detail:
  hdr/StaticWS - Reserve workspace for QA7 peripheral address, HAL-wide spinlock, and doorbell device
  Makefile, s/DBell - Add doorbell device implementation
  hdr/BCM2835 - Clean up dead macros, add new macros for spinlock claim/release and basic CPU detection. Define new IRQ numbers for the "QA7" peripheral.
  hdr/CastleMacros, s/Top - Generate two HAL descriptors and entry point tables: One for single-core machines and one for multi-core machines. This avoids some MP-related overheads on ARM11 models of Pi. Implement SMP HAL entry points.
  s/Interrupts - Add support for the QA7 interrupts. Although some interrupts can be flexibly routed to different cores, we currently stick with a static scheme.
  s/Messaging - Use CPUDetect macro
Admin:
  Untested
  Requires Kernel-6_09


Version 0.76. Tagged as 'BCM2835-0_76'

Detail:
  Firmware as of 28th July will allow the GPU to make use of the top 16MB of RAM in 1GB machines. This overlaps the ARM's IO space, essentially making that area of memory inaccessible to us.
  This causes problems because we rely on a couple of buffers which are located in VC memory (virtual GPIO buffer & FT5406 touchscreen buffer)
  At some point extra mailbox messages were added to allow the ARM to dictate the location of these buffers; so make use of those messages wherever possible.
  File changes:
  s/Messaging - Remove VirtGPIOBuf and TouchBuf related tags from the initialisation tag sequence. Add new GetVCBuffer function that can be called post-MMU init to deal with getting/setting the buffer addresses.
  s/Top - Use GetVCBuffer to initialise VirtGPIOBuf
  s/Touch - Use GetVCBuffer to get touchscreen buffer
  hdr/StaticWS - Remove TouchBuf from workspace, no longer needed
Admin:
  Tested on Raspberry Pi 3 with firmware from March 2016 (Set commands not supported), 21st July 2017 (set commands supported, but upper 16MB not used), 28th July 2017 (set commands supported and necessary)


Version 0.71. Tagged as 'BCM2835-0_71'

The SDIO HAL device reports when it is sure fixed disc media is attached (ie. eMMC soldered on the same PCB) which causes SDFS to report this to FileCore as a fixed disc, skipping the removable safety checks.
However, CM3 and CM3L both return the same board id so we can't work out which is which. Additionally, someone could attach an external eMMC in theory on a custom expansion board (instead of an SD card socket like the CMIO has).
To resolve this, we assign IO expander line 6 of U8 to be a safety catch. If that line is held low, it signifies this is definitely a CM3 - in effect this is a "definitely has eMMC" or "maybe has eMMC" switch.

Tested on CM1, CM3, CM3L, and a suitably modified CM3 with the help of Chris Hall.

Version 0.69. Tagged as 'BCM2835-0_69'

Detail:
  Move the register accesses for GPIO to the HAL, since they are hardware specific.
  Add recognition of board types for Pi 3, Compute module 3, rev 3 Pi 0's, and the newer Pi 2's with BCM2837 on them.
Admin:
  Based in part on a submission from Tank.
  Tested on a Pi 2. Requires corresponding GPIO module (tag GPIO-1_00-1_11_2_1 or later).

Version 0.67. Tagged as 'BCM2835-0_67'

The Pi is unusual in self modifying the ROM image when a CMOS setting was changed (due to there being none on the PCB), with the potential of ending up with a corrupt OS image on disc.
Remove this code and emulate the CMOS using normal RAM, and using the Pi firmware to load the CMOS file in for us (like fatload does on OMAP based designs) by using its ability to load a second arbitrary file at an address, intended in the Linux world to load a disc image.

To use this you will need to add
  ramfsfile=CMOS
  ramfsaddr=0x508000
to config.txt which loads it 5MB (ie. ImageSize) above the default load address (&8000), though as noted in the changes to BCM2835-0_60 we don't really need to load at offset &8000 but generally do since that's the Pi firmware's default.

hdr/StaticWS:
New workspace to hold our CMOS copy.
CMOS.s:
Remove the 2k magic block, add a simple bytewise copy loop implementation.
SDIO.s:
Extend ADR range.
Top.s:
Copy what the Pi firmware loads somewhere safe until the MMU is on, then copy it back (converting from logical to physical order along the way).
Change other values recovered from pre-MMU times using advanced post indexed addressing technology (TM) rather than switching around sb a lot.

Tested on a Pi 3, with and without an initial CMOS file present.

Version 0.61. Tagged as 'BCM2835-0_61'

Detail:
  hdr/BCM2835, hdr/StaticWS, s/Debug, s/Top, s/Video - Fix up the two serial debug switches to work correctly. Disable debug by default.
  s/UART, hdr/UART - Implement HAL UART API, for the PL011 UART.
Admin:
  Tested on Raspberry Pi 1 B
  Requires DualSerial 0.25 to work correctly


Version 0.59. Tagged as 'BCM2835-0_59'

Detail:
  hdr/BCM2835 - Remove mailbox definitions - use the ones exported by BCMSupport to avoid needless duplication
  hdr/StaticWS, s/Messaging, s/Top - Use the mailbox property interface to request & map in the virtual GPIO buffer (if present)
  s/SDIO - On the Pi 3B, the GPIO that was used for the SD activity GPIO is now used for a different purpose. To control the activity LED we need to go via an I2C attached GPIO extender, which itself is exposed to the ARM via the new "virtual GPIO" buffer
  s/VCHIQ - Update to use BCMSupport mailbox definitions
Admin:
  Tested on Pi 1B, 3B


Version 0.54. Tagged as 'BCM2835-0_54'

Detail:
  s/Messaging - Ensure the PL011 UART module clock is set to 3MHz on startup, in order to allow the debug terminal to work
  hdr/StaticWS, s/Top - Add a basic HAL device to expose the GPU mailboxes
Admin:
  Tested on Raspberry Pi 1B/2B/3B
  Fixes garbled debug terminal input/output on Pi 3


Version 0.52. Tagged as 'BCM2835-0_52'

Detail:
  Makefile, s/Touch - Basic HAL device for the official touchscreen, which just exposes the address of the buffer which the GPU periodically fills with a register dump of the touchscreen controller.
  hdr/BCM2835 - Remove old comment. Add new tag for getting the touchscreen buffer address.
  hdr/StaticWS - Remove old workspace entries. Add new entries for touchscreen.
  s/Messaging - Remove the messagebox tags which set a screen mode on startup (BCMVideo will handle that for us), and just blank the screen instead (to stop the GPU displaying a coloured square). Add tag to get the touchscreen buffer address.
  s/Top - Register touchscreen HAL device during HAL_InitDevices. Remove more old code.
Admin:
  Tested on Raspberry Pi 1 B


Version 0.50. Tagged as 'BCM2835-0_50'

Detail:
  hdr/StaticWS, s/Top - Removed code to map in all of VC memory. Currently nothing needs it, and the code was broken anyway (debug output would corrupt a1 value given to OS_MapInIO)
Admin:
  Tested on Raspberry Pi


Version 0.46. Tagged as 'BCM2835-0_46'

Detail:
  s/SPI - Basic HAL devices for the 3 SPI controllers. These expose the register addresses & IRQ numbers, and (for SPI1 & SPI2) deal with enabling/disabling the hardware and the shared IRQ line. GPIO mapping currently isn't dealt with - we don't know which pin group to use (SPI0 can use two different sets on the compute) or how many chip select lines are desired.
  Makefile - Add SPI source
  hdr/BCM2835 - Add aux SPI registers
  hdr/StaticWS - Reserve workspace for the HAL devices
  s/Top - Register new devices in HAL_InitDevices
Admin:
  Tested on Raspberry Pi B & 2 B


Version 0.45. Tagged as 'BCM2835-0_45'

Detail:
  CJE's RTC module uses a DS1307-compatible RTC chip similar to the one used in the Iyonix. Previously the kernel handled talking to it, but now that low-level RTC handling has been moved out of the kernel we need an RTC HAL device in the BCM2835 HAL instead.
  s/RTC - A copy of s.RTC from the Tungsten HAL, relicensed as BSD with permission from Rob Sprowson
  Makefile, hdr/StaticWS, s/Top - Additional changes needed to hook the code into the HAL
Admin:
  Tested on Raspberry Pi, but without an RTC module fitted
  However the similarity of the clock chip to the one in the Iyonix should mean there's little chance of this code failing to work correctly when an RTC is fitted


Version 0.31. Tagged as 'BCM2835-0_31'

Detail:
  hdr/StaticWS, s/Top, s/Video - Added a simple VDU HAL device that exposes a DMA channel to BCMVideo for use with GraphicsV_Render
  hdr/BCM2835 - Don't allow DMA channel 12 to be used; latest firmware seems to have a bug which claims its free when in reality it isn't.
  s/Messaging, s/DMA - Adjust DMA init to allow the video device to claim a DMA channel before the DMA devices are initialised
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.25. Tagged as 'BCM2835-0_25'

Detail:
  hdr/BCM2835, hdr/StaticWS, s/IIC - On rev 2 boards the usage of BSC0 and BSC1 have been swapped, such that BSC1 is now sent to the expansion header instead of BSC0.
  To allow RISC OS to continue to work with clock chips and other hardware fitted to the header, expose BSC1 to RISC OS if on a rev 2 board, or BSC0 if on a rev 1.
Admin:
  Changes received from Dave Higton
  Tested by Dave on rev 1 & rev 2 boards, with IIC devices
  Tested by me on rev 1 board (with no IIC devices fitted)


Version 0.24. Tagged as 'BCM2835-0_24'

Read board model, revision, and available DMA channels from messaging channel. Report board revision via GPIO HAL device. Recover lost ROM relocation code.

Detail:
  hdr/StaticWS, s/Messaging, s/Top - Now reads board model, revision and available DMA channels from messaging channel
  hdr/StaticWS, s/GPIO - Updated GPIO HAL device to report board revision instead of a generic response of 'unknown'
  s/Top - Recovered ROM relocation code that got lost during a merge. End of ROM image no longer being corrupted, and RISC OS now sees correct amount of RAM.
  s/DMA - Ditch old code to read available DMA channels and use value read by HAL_QueryPlatform instead.
Admin:
  Tested on Raspberry Pi (B rev 1) with various start.elf sizes & versions
  DMA channel reporting only available with latest firmware (i.e. 8th Sep)
  Board revision number read by messaging channel seems to match that returned by /proc/cpuinfo on Linux


Version 0.22. Tagged as 'BCM2835-0_22'

Detail:
  Makefile, s/Display - Deleted on-screen debug code
  hdr/BCM2835, hdr/StaticWS, s/IIC, s/Messaging, s/Stubs, s/Top, s/UART - Strip out calls to on-screen debug code, and a few bits of video code
  s/Video - Video code removed and replaced with stub functions similar to other HALs. Only remaining useful code is HAL_Video_StartupMode, which in time should probably be moved to BCMVideo as well.
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.21. Tagged as 'BCM2835-0_21'

Detail:
  Implementation of the high-level HAL IIC interface provided by Dave Higton.
Admin:
  Checked it builds and runs at ROOL.

Version 0.20. Tagged as 'BCM2835-0_20'

Add GPIO & VCHIQ HAL devices. Fix FlushDataCache macro to perform a clean & invalidate instead of just an invalidate.

Detail:
  s/GPIO - Basic implementation of the GPIO HAL device to allow the GPIO module to detect the board type
  s/VCHIQ, hdr/StaticWS - New VCHIQ HAL device which exposes the functionality required by the work-in-progress VCHIQ driver.
  Makefile, s/Top - Hook up the new files/devices
  hdr/BCM2835 - Make the FlushDataCache macro perform a clean & invalidate, to match the behaviour of FlushDataCacheRange
Admin:
  Tested on Raspberry Pi with high processor vectors


Version 0.17. Tagged as 'BCM2835-0_17'

        HAL_MachineID functioning correctly
Admin:


Version 0.15. Tagged as 'BCM2835-0_15'

Detail:
	HAL_Reset now causes a complete reboot of the machiine. It isnt yet properly called from
	the kernel.. I've not investigated why yet. Behaviour tested using OS_Hardware call

	HAL_MachineID, with the github start.elf from 18 July 2012 will provide a valid MAC address ..
	i.e. that specific to this machine. The a1 value in HAL_ExtendedID needs to be set 0 for this to be reported
	by OS_ReadSysInfo .. unfortunately, again at this stage, it stalls the boot when set 0, so just for now
	the committed value for a1 in HAL_ExtendedID is not 0 .

	centralised messaging routine added. This is used a fair bit in acquiring the operating environment
	Not yet used in the DMA stuff. probably ought to be. At present the messaging channel this mainly
	handles is not complete, so information from this code is still WIP

Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.14. Tagged as 'BCM2835-0_14'

Detail:
  s/DMA, hdr/DMA, Makefile - DMA driver, as an implementation of the DMA controller and list type DMA channel HAL devices
  hdr/StaticWS - Added DMA workspace definition
  hdr/BCM2835 - Removed DMA control block definition (now in hdr/DMA). Add definitions for the mailbox property interface, which should be supported by the GPU firmware sometime soon.
  s/Top - Export a couple of the debug functions. Store logical & physical address of NCNB workspace instead of hackily getting phys addr of the (cacheable) HAL workspace. Call DMA_InitDevices in HAL_InitDevices.
Admin:
  Tested in BCM2835 ROM
  DMA driver hasn't received large amounts of testing, lacks support for finite-length circular transfers, and currently only has one DMA channel enabled
  More DMA channels should be available once the mailbox property interface is functional and we know which channels the GPU does and doesn't use.


Version 0.11. Tagged as 'BCM2835-0_11'

Detail:
  * Engage the GPIO controller's pull-up resistors on SDCLK, CMD and DAT0-DAT3.
    In tests, this seems to address the worst of the unreliability we have
    seen previously.
  * Remove the entry to change the bus between push-pull and open-drain modes.
    The BCM2835 simply doesn't seem to be able to do this. Fortunately, all
    the cards I have tested seem to be OK with the GPIO controller's pull-up
    on the CMD line (however strong that is - it's undocumented) engaged at
    all times.
  * Time a dummy command in order to calculate the speed of the input clock
    to the SD controller block (there doesn't appear to be any way to read
    its speed directly!) This is necessary because recent versions of the
    firmware have not only changed the default clock speed, but even made it
    a user-configurable option in config.txt. It's very important that we
    know how fast it is - if we set the dividers so SDCLK is too slow, then
    the workaround for the register write bug won't work, too fast and we
    overclock the cards, potentially damaging them.
  * Re-enable high speed mode. As long as we don't use the High Speed Enable
    bit in Host Control 1 (see change in SDIODriver 0.03) this seems to work
    for me.
Admin:
  Tested against my collection of test cards on a Raspberry Pi with the
  firmware from the 2012-06-22 commit on github, and with
  init_emmc_clock=100000000 in config.txt (though other values, or the
  absence of that line, or the entire file, should also work). The only
  issues I had appeared to be due to mechanical problems with the SD socket,
  and went away after the card was reseated one or more times.

Version 0.10. Tagged as 'BCM2835-0_10'

Detail:
  * Bugfix to HAL_FIQDisableAll - it wasn't clearing the FIQ register (would
    only have caused trouble in practice if the same device was subsequently
    enabled as an IRQ).
  * Added a load of memory barriers to s.Interrupts and s.Timers to conform
    to the requirement stated in 1.3 of the datasheet.
  * Added a HAL device for the Arasan SDHCI controller. Note that this does
    not currently work reliably, and results vary from card to card. High
    speed support is currently disabled until we are able to verify that it
    works reliably.
  * Added a sprinkling of "GET Hdr:ListOpts" because the space reserved for
    the SDHCI HAL device in hdr.StaticWS is determined by including
    Hdr:HALDevice and Hdr:SDHCIDevice, which need it.
  * When support for saving "CMOS" to the SD card is added, the ROM image
    file (kernel.img) is the only one we can count on the bootloader
    installing in memory, so I think we're going to have to work using the
    table in s.CMOS. Broadcom seems to like messing around with the space
    just after the processor vector table, so rather than adding a pointer
    to the table there, I've opted to mark it using a magic word.
Admin:
  Tested on a Raspberry Pi - as noted above, there are reliability issues.

Version 0.09. Tagged as 'BCM2835-0_09'

Detail:
  Substituted remaining hard spaces with normal ones and expanded tabs.
  This now matches the de facto standard for other components, and also looks
  better in the CVS web viewer.
Admin:
  No code changes

Version 0.06. Tagged as 'BCM2835-0_06'

Detail:
 * Moved interrupt and timer code out of s.Stubs - they're not stubs any more.
 * Rewrote timer and counter code to use GPU system timer 1 for our Timer0
   rather than the ARM timer. This is recommended in the Broadcom datasheet
   because it's driven from the APB clock and so its speed will vary in
   reduced or low power mode.
 * HAL_CounterDelay now, well, does a delay!
 * Added a Timer1, driven from GPU system timer 3 - common code with Timer0.
 * Reshuffled device numbers so the GPU interrupts are at the bottom. This
   works better for FIQs and makes Timer0 the lowest priority interrupt.
 * Higher device numbers are now consistently treated as higher priority.
 * Stopped using bits 8-31 of the basic interrupt registers. These can't be
   masked, so they cause the kernel to lock up if generated, which happens
   if the GPU interrupt which they alias is generated (which appears to
   include the timers even though this is not documented).
 * Added definitions for all the interrupts, including those redacted from the
   datasheet - we need them at least for timers, USB and SD.
 * Stopped HAL_IRQClear from doing anything - this interrupt controller
   doesn't do latching. To acknowledge timer interrupts, you should use
   HAL_TimerIRQClear (and HAL_IRQClear too for compatibility with other ports).
 * Implemented HAL_IRQStatus and all the FIQ control routines.
 * Offsets to interrupt controller registers now use symbolic names.
 * Replaced some hard spaces in sources with normal ones.
Admin:
  Tested on a beta Raspberry Pi. Confirmed that interrupt handlers for both
  ARM and GPU sources can both be operational simultaneuosly. However, the FIQ
  code has not been tested. Timer0 is verified as running at the correct
  speed and reporting a count *down* in the correct range (not a count up as
  some previous versions did). HAL_CounterDelay appears correct also.

Version 0.04. Tagged as 'BCM2835-0_04'

Detail:
   Recent changes in the broadcom startup code now accomodated. frame buffer
   will now determine whether it is L2 cached or not, and be set up accordingly.
   ATAGs not currently read, so ram size defaulted.
  ** note that there will be further updates to this over the following days
  ** trackikng startup code changes.
   added HAL_TimerIRQClear entry
Admin:
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 0.03. Tagged as 'BCM2835-0_03'

  Will now compile against initial developemnt start.elf, and against the
  start.elf in general release at this date. (compile switch UseALBlob in
  hdr.BCM2835). Extended header defs, Updated IRQ stuff, HAL_FramebufferAddress
  Reworked Timers, + a number of other bits. Still work in progress.
Detail:
  (list files and functions that have changed)
Admin:
  Compiled and working - as far as it goes -. Will enable use with the current
  start.elf, and is (subject to any minor changes introduced) ready for use with the
  version due for release shortly which will provide the correct transparency operation,
  and a better aligned frame buffer

Version 0.02. Tagged as 'BCM2835-0_02'

Detail:
  Covers the basic functionality, but does require a customised start.elf
  to function. The vast majority is an entirely new implementation and is
  BSD licenced, but 4% (the Makefile and a handful of simple macros) are
  copied from pre-existing Castle-licenced code, so it lives under the
  "mixed" hierarchy. If other HALs are anything to go by, we'll end up
  having to add more Castle code (at least some C runtime functions) so it's
  probably juast as well.
Admin:
  Code received from Adrian Lees