1. 06 Mar, 2020 1 commit
  2. 21 Feb, 2020 1 commit
  3. 18 Feb, 2020 18 commits
    • Robert Sprowson's avatar
      More sensible abstraction · 76cb713f
      Robert Sprowson authored
      Give the ISPENDRn address directly, since its only the HAL that knows that iDev_GPU is encoded from 64+, rather than having to bake it into DWCDriver.
    • Robert Sprowson's avatar
      Make a substitute for MPHI · b1d217a2
      Robert Sprowson authored
      The MPHI is (ab)used by DWCDriver as a means to do a FIQ downgrade to IRQ, but Pi 4 has no MPHI, so instead we substitute the GIC (as the GICD_ISPENDRn can be used to cause an IRQ from software).
    • Jeffrey Lee's avatar
      Let VCHIQ know which page list format to use · 34e39bc3
      Jeffrey Lee authored
      VCHIQ bulk transfers on Pi 4 use a different page list format, in order
      to allow for full use of the larger 36bit physical address space. Add a
      flags word to the VCHIQ HAL device so that we can let the VCHIQ module
      know what page list format it should use for the machine we're running
    • Robert Sprowson's avatar
      Extend the PCI address table for 64b · 5984aed1
      Robert Sprowson authored
      The USB controller is at physical addresses outside 32b range, extend so that it can be picked up by PCI manager, and hence use its SWIs (rather than *Memory P) to see registers.
      Also write the interrupt number into the config space so it can be picked up.
      Requires PCI-0_18.
    • Robert Sprowson's avatar
      Add remaining PCIe setup steps · 0eae18b2
      Robert Sprowson authored
      Memory window now enabled on the VIA VL805, on-chip bridge set to forward memory transactions, ARM CPU to PCI address space translated.
      Since we know there's only the VIA chip on the bus, there's no dynamic probing going on like platforms that have PCI sockets. Its BAR settings are derived from defines at the top of PCI.s, so to browse the XHCI capability registers just peek at
        *Memory p 600100000 +20
      Only 1 of the 4 address space translation windows is used.
    • Robert Sprowson's avatar
      Add EtherNIC HAL device · b4504f00
      Robert Sprowson authored
      Basic HAL device to expose the GENET peripheral for the driver.
    • Robert Sprowson's avatar
      Add preliminary PCIe setup steps · 58c2c84e
      Robert Sprowson authored
      Just enough pokes to be able to scan configuration space such that the VIA XHCI controller can be seen by PCI Manager. Note: at present there are no memory or IO windows open, so you can't (yet) see XHCI registers.
    • Jeffrey Lee's avatar
      Add GIC interrupt controller support for BCM2838. · c821ef59
      Jeffrey Lee authored
      * Requires 'enable_gic=1' in config.txt (or Pi4 dtb to be present?)
      * IRQs are managed via the GIC, FIQs via the BCM2838 FIQ controller
      * Implemented in s.IntVC6 to avoid making s.Interrupts too
      * Previous VC6 interrupt support removed from s.Interrupts
      * From the OS's perspective, interrupt numbers mostly remain
      unchanged. However iDev_QA7 interrupts are unavailable, and some of
      the BCM2838 interrupts have been overlaid ontop of them.
      * Device drivers must take care to issue HAL_IRQClear, as that is
      a new requirement for this HAL
    • Jeffrey Lee's avatar
      Fix debugging via UART0 · a634aca4
      Jeffrey Lee authored
      HAL_QueryPlatform was attempting debug output before the debug
      UART had been initialised. Since both the PL011 & MiniUART
      configuration depends on getting/setting firmware values, fix it
      by just removing the debug prints from HAL_QueryPlatform.
    • Ben Avison's avatar
      Support >1GB RAM · 8d1e74f8
      Ben Avison authored
      RAM sizes above 1GB are not reported by the usual mailbox property, and it
      seems unlikely that this will change because the VC RAM allocation has to
      remain within the bottom 1GB of the address space (the VC still uses the
      upper two bits of its addresses for cache policy) and this property cannot
      describe a non-contiguous range. Use the board revision bitfield to recognise
      when additional general-purpose RAM exists above the VC allocation. For now,
      we're running in "low peripherals" mode, so the top 64MB of 4GB RAM machines
      is inaccessible. If the VC allocation is also 64MB, that means the startup
      banner of Pi 4 will read 960MB, 1984MB or 3968MB.
      Also fix HAL_PhysInfo (and by implication, OS_Memory 6 and 7) to report the
      full 35-bit physical address space on Pi 4. The `range` struct filled in by
      HAL_PhysInfo has not been extended to 64-bit physical addresses because it
      describes RAM, and for now at least, RAM just squeezes into 32-bit addresses.
    • Ben Avison's avatar
      Support EMMC2 controller · 8c95c72e
      Ben Avison authored
      This controller is now preferred over the legacy EMMC controller, and it is
      capable of UHS speeds (pending support in SDIODriver).
      Requires RiscOS/Sources/HWSupport/SD/SDIODriver!4
    • Ben Avison's avatar
      Extended IRQ support, and FIQ support · 21977fe8
      Ben Avison authored
      Both still use GIC bypass mode. Assuming for now that extended GPU peripherals
      can't support FIQ without GIC (it seems as though they either all use IRQ or
      all use FIQ, and RISC OS isn't set up for there being multiple FIQ sources
      active at once).
    • Ben Avison's avatar
      SD bugfixes · 40b661d1
      Ben Avison authored
      * Implement SD activity LED for Pi 4
      * Remove inappropriate reprogramming of GPIO47 for Pi 3 B(+) and A+
      * Correct the value for SDHCIWriteInterval which is used during SetSDCLK()
    • Ben Avison's avatar
      GPIO support · 987b080d
      Ben Avison authored
      * Board recognition for Pi 4
      * Updated the pin enumeration table to specify new functions available in Pi 4
        (I2C[3456], SPI[3456], UART[2345])
    • Ben Avison's avatar
      Enable SD controller · 0d6ff642
      Ben Avison authored
      * Efforts to get the faster EMMC2 controller working are ongoing. In the
        meantime, this enables the backward-compatible EMMC1 controller.
      * The method required to control the activity LED appears to have changed,
        yet again. I haven't worked out how yet, so this is currently
    • Ben Avison's avatar
      Get IRQs working · 72381d68
      Ben Avison authored
      * For now, this uses the legacy interrupt controller, whose register layout has
        unfortunately changed in some unhelpful ways. There is also a GICv2 in the
        SoC, which we will need to transition across to in order to use some of the
        newer peripherals (including USB3 and gigabit Ethernet).
      * This requires a corresponding set of changes to start.elf: substitute all
        three instances of &E30011E7 with &E3001000.
      * FIQs are not currently supported, as the legacy interrupt controller has
        changed how these are handled. It seems likely that we'll transition to
        GIC before too long, which means it's not worth bothering to implement them
        for the legacy interrupt controller.
    • Ben Avison's avatar
      Minimal read-write support for mini-UART · eed3f44e
      Ben Avison authored
      Because the mini-UART clock is derived from the core clock, and this varies
      by hardware platform and even firmware version, move the initial mailbox
      read to before UART initialisation so that this information is available.
    • Ben Avison's avatar
      Peripheral physical addresses have moved again · 67d46df6
      Ben Avison authored
      * the IO region previously used only for the QA7 extensions now holds a GIC
        as well on Pi 4, so give it a more generic name
      * there's a new, second peripheral IO region to map in as well
  4. 05 Feb, 2020 1 commit
    • Robert Sprowson's avatar
      Fix OS_SerialOp default handshaking use on Pi · 0b2f7c19
      Robert Sprowson authored
      The default state for the Serial device (aka OS_SerialOp, and redirection to serial via *FX) is to expect hardware handshaking. However the implementation of HAL_UARTModemStatus when ModemControl = {FALSE} state didn't set a return value so ended up returning a1 = the port number (=0) rather than valid status bits. In turn, DualSerial took that to mean CTS/DSR deasserted and refused to send anything.
      To a lesser extent HAL_UARTModemControl also affected, returning a1 = port number 0 too.
      For both, set a return value; the value is as though a cable is always present with RTS=CTS and DTR=DSR.
      Also, fix the bugs in ModemControl = {TRUE}. This also fakes DTR=DSR which status/control bits don't appear to be implemented in the UART peripheral. Tested briefly, checking CTS state when plugging/unplugging a cable.
      Version 0.82. Tagged as 'HAL_BCM2835-0_82'
  5. 10 Aug, 2019 1 commit
    • Ben Avison's avatar
      Set shareability bit in page tables for IO region on Pi 2 onwards · 699a746a
      Ben Avison authored
      RISCOS_MapInIO does relatively little processing on the L1PT flags that the
      HAL passes to it. However, when modules come along later and try to locate
      IO again, using OS_Memory 13, access permissions are specified using a
      variation on dynamic area flags. The kernel translates from these to L1PT
      flags, and one of the rules it applies is that the shareability bit is set
      if on a multiprocessor system. On Pi 2 and later, this means it doesn't find
      a match amongst the sections that were mapped in by the HAL, and in practice
      this means BCMVideo ends up causing 16MB of IO space to be mapped in twice.
      Fix this by passing the L1_S flag to RISCOS_MapInIO on Pi 2 and later. This
      effectively frees up an additional 16MB of logical address space for dynamic
      Version 0.81. Tagged as 'HAL_BCM2835-0_81'
  6. 02 Aug, 2019 1 commit
    • Ben Avison's avatar
      Address of mailbox given to GPU should have cacheability bits set correctly · 34d04d6b
      Ben Avison authored
      On entry to HAL_SendHostMessage, we ensure the contents of the mailbox buffer
      are flushed out to the ARM L2 cache (if applicable) and main memory. There
      were a couple of instructions to fill in the top two bits of the address
      before passing it to the VC, but they were commented out for reasons that are
      not clear.
      The effect of this is that the VC will look in its L1 and L2 caches for the
      data in the buffer. On Pi 1 and 0, this wouldn't be too bad, since ARM11
      didn't have its own L2 cache and would have written the data into the VC L2
      cache instead, meaning that there would only be coherencency problems if the
      VC L1 cache still contained the old contents of the address. On Pi 2-4, it's
      more risky, because the VC L2 cache could also be inconsistent with main
      memory at this point.
      Reinstating the top two bits doesn't appear to cause any ill effects I can
      see (tested on Pi 1 and 4), so put these instructions back in.
      Version 0.80. Tagged as 'HAL_BCM2835-0_80'
  7. 20 May, 2019 1 commit
    • Robert Sprowson's avatar
      Add Compute Module 3+ support · 12a389b2
      Robert Sprowson authored
      GPIO.s,hdr/BCM2835: Table of known ids updated
      SPI.s: Fix long broken compute module support (only the original CM1 would have exported SPI2 due to not checking for the new id scheme).
      Unrelated, SDIO.s: Use CallOS macro.
      Thanks to Chris Hall for testing this on a CM3+ 8GB model.
      Version 0.79. Tagged as 'HAL_BCM2835-0_79'
  8. 25 Feb, 2019 1 commit
    • Robert Sprowson's avatar
      Check Board_Model only once · 7c2fe7dc
      Robert Sprowson authored
      Do an upfront check for the model being 0, if that ever changes there's probably something seriously different. Look only at the Board_Revision elsewhere.
      Add the other Compute module to the SPI2 check (though currently the checks don't consider "New" revision words).
      Version 0.78. Tagged as 'BCM2835-0_78'
  9. 01 Dec, 2018 1 commit
    • Robert Sprowson's avatar
      Appease Thor · 9a2c1030
      Robert Sprowson authored
      SDIO.s: a condition code mixup meant that during intense SD card activity the thunder bolt symbol would appear due to poking the non-LED lines on 3B+
      GPIO.s: extend the 'free for use' table to include 3A+ pins, otherwise it read off the end; add an ASSERT to catch this in future
      Version 0.77. Tagged as 'BCM2835-0_77'
  10. 26 Oct, 2018 1 commit
  11. 07 Jul, 2018 1 commit
    • Jeffrey Lee's avatar
      Merge SMP branch to trunk · 06491820
      Jeffrey Lee authored
        hdr/StaticWS - Reserve workspace for QA7 peripheral address, HAL-wide spinlock, and doorbell device
        Makefile, s/DBell - Add doorbell device implementation
        hdr/BCM2835 - Clean up dead macros, add new macros for spinlock claim/release and basic CPU detection. Define new IRQ numbers for the "QA7" peripheral.
        hdr/CastleMacros, s/Top - Generate two HAL descriptors and entry point tables: One for single-core machines and one for multi-core machines. This avoids some MP-related overheads on ARM11 models of Pi. Implement SMP HAL entry points.
        s/Interrupts - Add support for the QA7 interrupts. Although some interrupts can be flexibly routed to different cores, we currently stick with a static scheme.
        s/Messaging - Use CPUDetect macro
        Requires Kernel-6_09
      Version 0.76. Tagged as 'BCM2835-0_76'
  12. 10 Apr, 2018 1 commit
    • Robert Sprowson's avatar
      Debug UART typo & clarification · 8c7c60d9
      Robert Sprowson authored
      Top.s: HAL_UARTStartUp takes 0's based UART numbers, so the debug setup would go wrong (if HAL_UARTStartUp actually checked the value).
      UART.s: Re-express the baud register default value so its origin is clear.
      Retagged as BCM2835-0_75 as the (non-debug) version is binary identical.
  13. 21 Mar, 2018 1 commit
    • Robert Sprowson's avatar
      Safe GPIO pins table updates · b0ddf21a
      Robert Sprowson authored
      Add Pi3 B+ and Zero W.
      Split out CM3 from CM1, since the CM3 reuses some high GPIO lines as bit bashed SMPSU IIC bus, so we can't offer those for GPIO like on CM1.
      Version 0.75. Tagged as 'BCM2835-0_75'
  14. 19 Mar, 2018 1 commit
    • Jeffrey Lee's avatar
      Fix SD activity LED on 3B+ · f90ce9ec
      Jeffrey Lee authored
        hdr/BCM2835 - Add some new board revision values
        s/SDIO - Treat the 3B+ the same as the 3B when handling the activity LED. Also detect the Embest-manufactured CM1 and treat it the same as the Sony one.
        Tested on Raspberry Pi 3B+
      Version 0.74. Tagged as 'BCM2835-0_74'
  15. 09 Sep, 2017 2 commits
    • Jeffrey Lee's avatar
      Fix keyboard scan dependencies · 640e2cc1
      Jeffrey Lee authored
        s/KbdScan - Add RTSupport to the list of modules (dependency of DWCDriver)
        Tested on Raspberry Pi 3
      Version 0.73. Tagged as 'BCM2835-0_73'
    • ROOL's avatar
      Participate in keyboard scan dependencies · 14f24328
      ROOL authored
        Add keyboard scan code with list of modules that the kernel needs to do the same.
        Reorder the HALEntries to match Kernel-5_89.
        Remove unused stub functions (now KbdScan exists).
        Submission for USB bounty.
      Version 0.72. Tagged as 'BCM2835-0_72'
  16. 31 Jul, 2017 1 commit
    • Jeffrey Lee's avatar
      Fix compatibility with latest firmware · d58d5839
      Jeffrey Lee authored
        Firmware as of 28th July will allow the GPU to make use of the top 16MB of RAM in 1GB machines. This overlaps the ARM's IO space, essentially making that area of memory inaccessible to us.
        This causes problems because we rely on a couple of buffers which are located in VC memory (virtual GPIO buffer & FT5406 touchscreen buffer)
        At some point extra mailbox messages were added to allow the ARM to dictate the location of these buffers; so make use of those messages wherever possible.
        File changes:
        s/Messaging - Remove VirtGPIOBuf and TouchBuf related tags from the initialisation tag sequence. Add new GetVCBuffer function that can be called post-MMU init to deal with getting/setting the buffer addresses.
        s/Top - Use GetVCBuffer to initialise VirtGPIOBuf
        s/Touch - Use GetVCBuffer to get touchscreen buffer
        hdr/StaticWS - Remove TouchBuf from workspace, no longer needed
        Tested on Raspberry Pi 3 with firmware from March 2016 (Set commands not supported), 21st July 2017 (set commands supported, but upper 16MB not used), 28th July 2017 (set commands supported and necessary)
      Version 0.71. Tagged as 'BCM2835-0_71'
  17. 27 Jul, 2017 1 commit
  18. 14 May, 2017 1 commit
    • Robert Sprowson's avatar
      Add new scheme ids for A+ and B+ to id table · 2e99b15b
      Robert Sprowson authored
      Apparently there are some A+ 1.1 and B+ 1.2's in the wild not built with their former id's (0x12 and 0x13) but using the newer 24 bit id scheme. Add aliases for these.
      Version 0.70. Tagged as 'BCM2835-0_70'
  19. 21 Feb, 2017 4 commits
    • Robert Sprowson's avatar
      Add support for CM3 and CM3L with or without eMMC · 6eeefb37
      Robert Sprowson authored
      The SDIO HAL device reports when it is sure fixed disc media is attached (ie. eMMC soldered on the same PCB) which causes SDFS to report this to FileCore as a fixed disc, skipping the removable safety checks.
      However, CM3 and CM3L both return the same board id so we can't work out which is which. Additionally, someone could attach an external eMMC in theory on a custom expansion board (instead of an SD card socket like the CMIO has).
      To resolve this, we assign IO expander line 6 of U8 to be a safety catch. If that line is held low, it signifies this is definitely a CM3 - in effect this is a "definitely has eMMC" or "maybe has eMMC" switch.
      Tested on CM1, CM3, CM3L, and a suitably modified CM3 with the help of Chris Hall.
      Version 0.69. Tagged as 'BCM2835-0_69'
    • Robert Sprowson's avatar
      Refactor early GPU queries · e65005cf
      Robert Sprowson authored
      Remove the baffling double indirection of RamAd (and unused exports SerNo and MacAdd), and treat these the same as the other pre-HAL_Init query results.
      This means the scope of the tagbuffer is limited to Messaging.s, rather than having to be kept preserved globally.
      Use memcpy() to copy tag list to tagbuffer for clarity.
      Tested on a Pi 3.
      Version 0.68. Tagged as 'BCM2835-0_68'
    • Robert Sprowson's avatar
      Fix for register corruption · 62e5efb4
      Robert Sprowson authored
      In HAL_QueryPlatform a mixture of register naming overlooks r6 (aka v3) gets used, but not preserved.
      Uppercase opcodes, add a few more comments around the CRC calculation.
    • Robert Sprowson's avatar
      Correct a couple of comments · 4a8fd0a1
      Robert Sprowson authored
      Some misleading notes about IIC0, and other minor clarifications.