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Memory window now enabled on the VIA VL805, on-chip bridge set to forward memory transactions, ARM CPU to PCI address space translated.
Since we know there's only the VIA chip on the bus, there's no dynamic probing going on like platforms that have PCI sockets. Its BAR settings are derived from defines at the top of PCI.s, so to browse the XHCI capability registers just peek at
  *Memory p 600100000 +20
Only 1 of the 4 address space translation windows is used.

Just enough pokes to be able to scan configuration space such that the VIA XHCI controller can be seen by PCI Manager. Note: at present there are no memory or IO windows open, so you can't (yet) see XHCI registers.