Commit edb5f642 authored by John Ballance's avatar John Ballance
Browse files

Detail: Frame buffer allocation via message channel almost complete. working

        HAL_MachineID functioning correctly
Admin:


Version 0.15. Tagged as 'BCM2835-0_15'
parent ef241880
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.14"
Module_Version SETA 14
Module_MajorVersion SETS "0.15"
Module_Version SETA 15
Module_MinorVersion SETS ""
Module_Date SETS "19 Jul 2012"
Module_ApplicationDate SETS "19-Jul-12"
Module_Date SETS "22 Jul 2012"
Module_ApplicationDate SETS "22-Jul-12"
Module_ComponentName SETS "BCM2835"
Module_ComponentPath SETS "mixed/RiscOS/Sources/HAL/BCM2835"
Module_FullVersion SETS "0.14"
Module_HelpVersion SETS "0.14 (19 Jul 2012)"
Module_FullVersion SETS "0.15"
Module_HelpVersion SETS "0.15 (22 Jul 2012)"
END
/* (0.14)
/* (0.15)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.14
#define Module_MajorVersion_CMHG 0.15
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 19 Jul 2012
#define Module_Date_CMHG 22 Jul 2012
#define Module_MajorVersion "0.14"
#define Module_Version 14
#define Module_MajorVersion "0.15"
#define Module_Version 15
#define Module_MinorVersion ""
#define Module_Date "19 Jul 2012"
#define Module_Date "22 Jul 2012"
#define Module_ApplicationDate "19-Jul-12"
#define Module_ApplicationDate "22-Jul-12"
#define Module_ComponentName "BCM2835"
#define Module_ComponentPath "mixed/RiscOS/Sources/HAL/BCM2835"
#define Module_FullVersion "0.14"
#define Module_HelpVersion "0.14 (19 Jul 2012)"
#define Module_LibraryVersionInfo "0:14"
#define Module_FullVersion "0.15"
#define Module_HelpVersion "0.15 (22 Jul 2012)"
#define Module_LibraryVersionInfo "0:15"
......@@ -30,10 +30,6 @@
; its Linux drivers, thus making this port possible.
;
; on the prototype (UseALBlob==TRUE)
; VideoCore sets up the following address windows for use by the ARM core:
; - &08000000 -> &7E000000 : 4MB window granting access to peripherals
; - &08800000 -> &7E800000 : 4MB window granting access to USB peripheral
[ :LNOT :DEF: BCM2835_Hdr
GBLL BCM2835_Hdr
......@@ -54,10 +50,6 @@ SCR32 SETL {TRUE}
Debug SETL {TRUE}
; Delay macro for really short delays
; RPi ARM11 registers
; 4Gbytes of address space.
......
......@@ -72,6 +72,7 @@ ARM_Counter_IO_Address # 4
ARM_Timer_IO_Address # 4
UARTFCRSoftCopy # 4
MMUOffBaseAddr # 4 ; original address kernel was loaded from
MachineID # 8 ; derived from MAC address if there
Timer SETA 0
WHILE Timer < NumTimers
......@@ -87,12 +88,12 @@ FB_CacheMode # 4
VC_Memory # 4
ARM_Memory # 4
; align to 16 byte boundary
; align to 16 byte boundary NB this isnt aligned once hal initialised
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
! 0,"tagbuffer at ":CC::STR:(&fc001000+:INDEX:@),0
tagbuffer # 256 ;; for now ; platform query buffer
; align to 16 byte boundary
; align to 16 byte boundary NB this isnt aligned once hal initialised
# (((:INDEX:@)+15):AND::NOT:15)-(:INDEX:@)
mbram # 0 ; structure needed for frame buffer descriptor
mbxres # 4
......@@ -102,7 +103,7 @@ mbyvres # 4
mbpitch # 4
mbbpp # 4
mbxoff # 4
myyoff # 4
mbyoff # 4
mbbase # 4
mbscrsz # 4
......@@ -129,6 +130,8 @@ PixelTable # 256*4
CurAddr # 4
CurHeight # 4
CurPalette # 4*4
vrmsize * :INDEX: @ - :INDEX:mbram
NCNBAddr # 4 ;NCNB workspace
NCNBPhysAddr # 4 ;VC physical address of NCNB workspace
......@@ -136,6 +139,8 @@ NCNBPhysAddr # 4 ;VC physical address of NCNB workspace
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
! 0,"SDHCI at ":CC::STR:(&FC0001D8+:INDEX:@),0
SDHCIWriteInterval # 4 ; minimum counter ticks between writes
SDHCILastWriteCount # 4 ; counter value at last write
......
......@@ -102,45 +102,140 @@ HAL_QueryPlatform ROUT
DCB "HalQueryPl",10,0
ALIGN
]
adrl r1, tagbuffer
mov r4, #GPU_L2CnonAl ; L2 Cache off mode
str r4, FB_CacheMode ; remember
adrl r1, tagbuffer
adr r0, tagb
mov r2, #tagslen
lp1 ldr r3, [r0], #4
lp1 ldr r3, [r0], #4 ; copy to workspace buffer
str r3, [r1], #4
subs r2, r2, #4
bgt lp1
mov r4, #&40000000 ; L2 Cache off mode
str r4, FB_CacheMode
adrl r1, tagbuffer
MOV r0, #MB_Chan_ARM2VC
BL HAL_SendHostMessage
BL HAL_SendHostMessage ; ask the questions
ADRL r0, tagbuffer
add r0,r0,#Dispbs-tagb
ADRL r5, tagbuffer ; now read the answers
ADD r0,r5,#Dispbs-tagb ; frame buffer address and size
LDMIA r0, {r1, r2}
STR r1, FB_Base
STR r1, mbbase
STR r2, FB_Size
STR r2, mbscrsz
[ HALDebug
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
]
add r0,r5,#phyx-tagb ; physical screen dimensions
LDMIA r0, {r1, r2}
STR r1, mbxres
STR r2, mbyres
[ HALDebug
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
]
add r0,r5,#virtx-tagb ; virtual screen dimensions
LDMIA r0, {r1, r2}
STR r1, mbxvres
STR r2, mbyvres
[ HALDebug
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
]
add r0,r5,#vxoff-tagb ; virtual screen offset
LDMIA r0, {r1, r2}
STR r1, mbxoff
STR r2, mbyoff
[ HALDebug
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
]
add r0,r5,#dispbpp-tagb ; bits per pixel
LDR r0, [r0]
; LDR r0, Dispbs
STR r0, mbbpp
[ HALDebug
bl HAL_DebugHexTX4
bl HAL_DebugHexTX4
]
STR r0, FB_Base
ADRL r0, tagbuffer
add r0, r0,#:INDEX:Dispsz-:INDEX:tagb
add r0,r5,#dispit-tagb ; display pitch
LDR r0, [r0]
; LDR r0, Dispsz
STR r0, mbpitch
[ HALDebug
bl HAL_DebugHexTX4
bl HAL_DebugHexTX4
]
; copy out and construct machine ID from MAC address
ADRL r0, tagbuffer
ADD r0, r0,#:INDEX:MAClo-:INDEX:tagb
ADRL a3, workspace
ADRL lr,MacAdd
LDR lr, [lr]
ADD a3, a3, lr
LDR lr, [a3, #-4] ; check if message completed
TST lr, #&80000000 ; NE if successful
MOVEQ a1, #0
MOVEQ a2, #0
LDMNEIA a3, {a1, a2}
AND a3, a1, #&ff000000
MOV a3, a3, LSR #24
ORR a2, a3, a2, LSL #8
MOV a1, a1, LSL #8
ORR a1, a1, #&81
BIC a2, a2, #&ff000000
; now encapsulate with crc
MOV a3, #0 ;
MOV a4, #7 ; number of bytes to do
gbyte ;
AND v2, a1, #&ff ; get next byte. shift reg round 8 byte
AND v3, a2, #&ff ; shift reg round 8 byte
MOV v1, v2, lsl #24
MOV v3, v3, lsl #24
ORR a1, v3, a1,lsr #8 ; shift reg round 8 byte
ORR a2, v1, a2,lsr #8 ; shift reg round 8 byte
EOR a3, a3, v2 ;
MOV v1, #8 ; number of bits to do
gbit ;
MOVS a3, a3, LSR #1 ; shift bit out into carry
EORCS a3, a3, #&8C ; feedback carry into other bits
SUBS v1, v1, #1 ; one less bit to do
BNE gbit ; loop until done whole byte
SUBS a4, a4, #1 ; one less byte to do
BNE gbyte ; loop until done all 7 bytes
AND v2, a1, #&ff ; get next byte. shift reg round 8 byte
AND v3, a2, #&ff ; shift reg round 8 byte
MOV v1, v2, lsl #24
MOV v3, v3, lsl #24
ORR a1, v3, a1,lsr #8 ; shift reg round 8 byte
ORR a2, v1, a2,lsr #8 ; shift reg round 8 byte
ORR a2, a2, a3, lsl #24 ; insert crc into hi byte
ADRL lr,MachineID
STMIA lr, {a1, a2}
[ HALDebug
bl HAL_DebugTXStrInline
DCB "HalQueryPldone",10,0
ALIGN
]
LDMFD R13!, {r0-r5, pc}
EXPORT MacAdd
EXPORT RamAd
EXPORT SerNo
EXPORT Displ
MacAdd DCD :INDEX:MAClo - :INDEX:tagb + :INDEX:tagbuffer
RamAd DCD :INDEX:ARMbs - :INDEX:tagb + :INDEX:tagbuffer
......@@ -182,25 +277,25 @@ tagdisplphyswh
DCD ARM2VC_Tag_FBSetPhysDimension
DCD 8
DCD 8
DCD 1920
phyx DCD 1920
DCD 1080
tagdisplvirtwh
DCD ARM2VC_Tag_FBSetVirtDimension
DCD 8
DCD 8
DCD 1920
virtx DCD 1920
DCD 1080
tagdisplvirtoffset
DCD ARM2VC_Tag_FBSetVirtOffset
DCD 8
DCD 8
DCD 0
vxoff DCD 0
DCD 0
tagdispldepth
DCD ARM2VC_Tag_FBSetDepth
DCD 4
DCD 4
DCD 32 ; 32bit
dispbpp DCD 32 ; 32bit
tagdisplpixord
DCD ARM2VC_Tag_FBSetPixelOrder
DCD 4
......@@ -215,7 +310,7 @@ taggetpitch
DCD ARM2VC_Tag_FBGetPitch
DCD 4
DCD 0
DCD 0
dispit DCD 0
tagdisplalloc
DCD ARM2VC_Tag_FBAlloc
DCD 8
......
......@@ -149,7 +149,6 @@
IMPORT HAL_QueryPlatform
EXPORT HAL_Base
IMPORT MacAdd
IMPORT RamAd
IMPORT SerNo
IMPORT Displ
......@@ -319,28 +318,12 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
LDR r0,=(16:SHL:MB_Pwr_USB)+MB_Chan_Pwr
BL HAL_SendHostMessage
; query the platform and set up a frame buffer.
BL HAL_QueryPlatform
ldr r1, =1920
str r1, mbxres
str r1, mbxvres
ldr r1, =1080
str r1, mbyres
str r1, mbyvres
[ SCR32
mov r1, #32
|
MOV r1, #16
]
str r1, mbbpp
ADD R4, R4, #MB_Base
ADR R0, mbram
ORR R2, R0, #GPU_L2CnonAl + MB_Chan_FB; try with L2 cache on
ORR R2, R0, #GPU_L2CnonAl + MB_Chan_FB; L2 cache on
MOV R0, R2
10
MOV r1, #0
BL HAL_SendHostMessage
......@@ -349,49 +332,36 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
mov r0,r3
bl HAL_DebugHexTX4
ldr r3, mbbase
and r1, r3, #GPU_CacheMask
str r1, FB_CacheMode
bl HAL_DebugHexTX4
bic r3, r3, #GPU_CacheMask
str r3, FB_Base
mov r0,r3
bl HAL_DebugHexTX4
[ HALDebug
[ SCR32
LDR R0,=1920*8*4
STR R3,ScreenBase ; for HAL use, remember address we were given
STR R0,BytesPerRow
MOV R0,#8*4
STR R3,ScreenBase ; for HAL use, remember address we were given
LDR r0,mbbpp
STR R0,BytesPerChar
|
LDR R0,=1920*8*2
STR R3,ScreenBase
LDR r3,mbxres
MUL r3, r0, r3
STR R0,BytesPerRow
MOV R0,#8*2
STR R0,BytesPerChar
]
MOV R0,#1920/8
1002 MOV R0, R3, LSR #3
STR R0,Columns
MOV R0,#1080/8
LDR R0, mbyres
MOV R0, r0, lsr #3
STR R0,Rows
MOV R0,#0
STR R0,InvertFont
STR R0,OutputX
STR R0,OutputY
[ SCR32
MOV R0,#&FF000000
MOV R1,#&FF000000
MOV R8,#32
|
MVN R0,#0
MOV R1,#0
MOV R0,R0,LSR #17
MOV R8,#16
]
LDR r8, mbbpp
CMP r8, #16
MOVGT R0,#&FF000000
MOVGT R1,#&FF000000
MVNLE R0,#0
MOVLE R1,#0
STR R8,BitsPerPixel
BL set_text_colours
......@@ -401,15 +371,13 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
LDR R3,Rows
BL clear_block
[ SCR32
MVN R0,#0
MOV R1,#&FF000000
LDR r8, mbbpp
CMP r8, #16
MVNGT R0,#0
MOVGT R1,#&FF000000
MOV R8,#32
|
MOV R0,#&1F<<10
MOV R1,#0
MOV R8,#16
]
MOVLE R0,#&1F<<10
MOVLE R1,#0
BL set_text_colours
MOV R0,#0
......@@ -423,24 +391,27 @@ start MSR CPSR_c,#F32_bit+I32_bit+SVC32_mode
]
]
ROMTOP * 6 <<20
RAMTOP * 128 <<20
ADRL a3, workspace
ADRL lr,RamAd
LDR lr, [lr]
ADD a3, a3, lr
LDMIA a3, {a1, a2}
LDMIA a3, {a1, a2} ; a1=base, a2=size
[ HALDebug
bl HAL_DebugTXStrInline
DCB "HalStartup3 .. rst rsz",10,0
ALIGN
bl HAL_DebugHexTX4 ; ram start
mov a1, a2
bl HAL_DebugHexTX4 ; ram end
mov a1, a3
bl HAL_DebugHexTX4 ; ram end
LDMIA a3, {a1, a2}
]
; debug hack to force 128meg ram and 6meg rom
MOV v2, #ROMTOP ;start of available RAM, after HAL + OS image
MOV a1, #RAMTOP ; end of RAM
; debug hack to force 128meg ram and 6meg rom
; MOV v2, #ROMTOP ;start of available RAM, after HAL + OS image
; MOV a1, #RAMTOP ; end of RAM
ADD v2, a1, #ROMTOP ; start of free ram
ADD a1, a2, a1 ; end of RAM
MOV a2, #0
MOV a3, #0
MOV a4, #0
......@@ -458,12 +429,23 @@ clear_lp
CMP a1, v2
BHI clear_lp
mov a2, v2
ADD a3, a2, #RAMTOP ; end of RAM
; a2 now -> first free ram location
ADRL a3, workspace
ADRL lr,RamAd
LDR lr, [lr]
ADD lr, a3, lr
LDR a3, [lr, #4] ; size
SUB a3, a3, #ROMTOP ; less what is used
ADD a3, a3, a2
[ HALDebug
bl HAL_DebugTXStrInline
DCB "HalStartup3 .. rst rend",10,0
ALIGN
mov a1,a2
bl HAL_DebugHexTX4
mov a1,a3
bl HAL_DebugHexTX4
]
MVN a4, #0
MOV a1, #0
STR a1, [sp, #-4]! ;reference handle (NULL for first call)
......@@ -669,6 +651,14 @@ HAL_Init
STR a3, FB_Size ; put in our workspace
STR a2, FB_Base ; for HAL_FramestoreAddress use
STR a1, FB_CacheMode
ADRL sb, workspace ; where we remembered it is
LDR a1, mbxres
LDR a2, mbyres
LDR a3, mbbpp
mov sb, a4
STR a1, mbxres
STR a2, mbyres
STR a3, mbbpp
; Get the physical address of NCNB workspace
; R8 -> start of NCNB workspace
......@@ -696,8 +686,6 @@ HAL_Init
; and initialise the display driver
LDR a3, FB_Size
LDR a2, FB_Base ; effectively part of the ROM image
; LDR a1, FB_CacheMode
; ORR a2, a2, a1 ; combine in the address we need 'the other side'
mov r0,a2
bl HAL_DebugHexTX4
mov r0,a3
......@@ -710,20 +698,17 @@ HAL_Init
STR a1,ScreenBase
bl HAL_DebugHexTX4
[ SCR32
LDR a1,=1920*8*4
STR a1,BytesPerRow
MOV a1,#8*4
STR a1,BytesPerChar
|
LDR a1,=1920*8*2
LDR a1,mbxres
LDR a2,mbbpp ;=1920*8*4
STR R2,BitsPerPixel
MUL a1, a2, a1
STR a1,BytesPerRow
MOV a1,#8*2
STR a1,BytesPerChar
]
MOV a1,#1920/8
STR a2,BytesPerChar
LDR a1,mbxres
MOV a1, a1, lsr #3
STR a1,Columns
MOV a1,#1080/8
LDR a1,mbyres
MOV a1, a1, lsr #3
STR a1,Rows
MOV a1,#0
STR a1,InvertFont
......@@ -731,17 +716,12 @@ HAL_Init
STR a1,OutputX
STR a1,OutputY
[ SCR32
MOV a1,#-1
MOV a2,#&FF000000
MOV R8,#32
|
MVN a1,#0
MOV a2,#0
MOV a1,a1,LSR #17
MOV R8,#16
]
STR R8,BitsPerPixel
CMP a2, #16
MOVGT a1,#-1
MOVGT a2,#&FF000000
MVNLE a1,#0
MOVLE a2,#0
MOVLE a1,a1,LSR #17
[ HALDebug
BL set_text_colours
......@@ -778,6 +758,7 @@ hal_init = " HAL Init completed",13,10,0
|
LDMFD R13!,{R8,PC}
]
MBAd DCD :INDEX:workspace + :INDEX:mbram
; Initialise and relocate the entry table.
......@@ -826,63 +807,16 @@ HAL_SuperIOInfo
MOV pc, lr
HAL_MachineID
STMFD sp!,{a3-a4,v1-v4,lr}
MOV a1, #0
MOV a2, #0
ADRL a3, workspace
ADRL lr,MacAdd
LDR lr, [lr]
ADD a3, a3, lr
LDR lr, [a4, #-4] ; check if message completed
TST lr, #&80000000 ; NE if successful
MOVEQ a1, #0
MOVEQ a2, #0
LDMEQFD sp!,{a3-a4,v1-v4,pc}; didn't read mac .. exit failed
LDMIA a3, {a1, a2}
AND a3, a1, #&ff000000
MOV a3, a3, LSR #24
ORR a2, a3, a2, LSL #8
MOV a1, a1, LSL #8
ORR a1, a1, #&81
BIC a2, a2, #&ff000000
; now encapsulate with crc
MOV a3, #0 ;
MOV a4, #7 ; number of bytes to do
gbyte ;
AND v2, a1, #&ff ; get next byte. shift reg round 8 byte
AND v3, a2, #&ff ; shift reg round 8 byte
MOV v1, v2, lsl #24
MOV v3, v3, lsl #24
ORR a1, v3, a1,lsr #8 ; shift reg round 8 byte
ORR a2, v1, a2,lsr #8 ; shift reg round 8 byte
EOR a3, a3, v2 ;
MOV v1, #8 ; number of bits to do
gbit ;
MOVS a3, a3, LSR #1 ; shift bit out into carry
EORCS a3, a3, #&8C ; feedback carry into other bits
SUBS v1, v1, #1 ; one less bit to do
BNE gbit ; loop until done whole byte
SUBS a4, a4, #1 ; one less byte to do
BNE gbyte ; loop until done all 7 bytes
AND v2, a1, #&ff ; get next byte. shift reg round 8 byte
AND v3, a2, #&ff ; shift reg round 8 byte
MOV v1, v2, lsl #24