Add preliminary PCIe setup steps

Just enough pokes to be able to scan configuration space such that the VIA XHCI controller can be seen by PCI Manager. Note: at present there are no memory or IO windows open, so you can't (yet) see XHCI registers.

Makefile

@@ -17,7 +17,7 @@
 
 COMPONENT = BCM2835 HAL
 TARGET = BCM2835
-OBJS = Top CLib CMOS Debug Interrupts SDIO Timers UART USB Video DMA Messaging GPIO VCHIQ IIC RTC SPI Touch KbdScan DBell IntVC6
+OBJS = Top CLib CMOS Debug Interrupts SDIO Timers UART USB Video DMA Messaging GPIO VCHIQ IIC RTC SPI Touch KbdScan DBell IntVC6 PCI
 
 HDRS =
 CMHGFILE =
@@ -27,8 +27,6 @@ ROM_TARGET = custom
 LNK_TARGET = custom
 AIFDBG    = aif._BCM2835
 
-#include StdRules
-#include StdTools
 include CModule
 
 CCFLAGS += -ff -APCS 3/32bit/nofp/noswst

VersionNum

@@ -4,18 +4,18 @@
  *
  */
 #define Module_MajorVersion_CMHG        0.82
-#define Module_MinorVersion_CMHG        Pi4.11
+#define Module_MinorVersion_CMHG        Pi4.12
 #define Module_Date_CMHG                18 Feb 2020
 
 #define Module_MajorVersion             "0.82"
 #define Module_Version                  82
-#define Module_MinorVersion             "Pi4.11"
+#define Module_MinorVersion             "Pi4.12"
 #define Module_Date                     "18 Feb 2020"
 
 #define Module_ApplicationDate          "18-Feb-20"
 
 #define Module_ComponentName            "HAL_BCM2835"
 
-#define Module_FullVersion              "0.82 (Pi4.11)"
-#define Module_HelpVersion              "0.82 (18 Feb 2020) Pi4.11"
+#define Module_FullVersion              "0.82 (Pi4.12)"
+#define Module_HelpVersion              "0.82 (18 Feb 2020) Pi4.12"
 #define Module_LibraryVersionInfo       "0:82"

hdr/BCM2835

@@ -932,7 +932,31 @@ GICC_DIR        * &1000
 V3D_Base     *        &00500000
 
 ; PCIe
-PCIe_Base    *        &01500000
+PCIe_Base                      * &01500000
+PCIe_BRIDGE_CFG                * 0
+PCIe_MISC_CTRL                 * &4008
+PCIe_MISC_CTRL_SCV_ACCESS_EN   * 1:SHL:12
+PCIe_MISC_CTRL_CFG_READ_SAFE   * 1:SHL:13
+PCIe_MISC_CTRL_MAX_BURST_SHIFT * 20
+PCIe_LINK_STATUS               * &4068
+PCIe_LINK_STATUS_PORT          * 1:SHL:7
+PCIe_LINK_STATUS_IN_L23        * 1:SHL:6
+PCIe_LINK_STATUS_DOWNLINK_ACT  * 1:SHL:5
+PCIe_LINK_STATUS_PHYLINK_UP    * 1:SHL:4
+PCIe_INTR2_STATUS              * &4300
+PCIe_INTR2_SET                 * &4304
+PCIe_INTR2_CLEAR               * &4308
+PCIe_INTR2_MASK                * &430C
+PCIe_INTR2_MASK_SET            * &4310
+PCIe_INTR2_MASK_CLEAR          * &4314
+PCIe_EXT_CFG_DATA              * &8000 ; Up to 4k of config space
+PCIe_EXT_CFG_INDEX             * &9000 ; Config space selector
+PCIe_EXT_CFG_INDEX_BUS_SHIFT   * 20
+PCIe_EXT_CFG_INDEX_DEV_SHIFT   * 15
+PCIe_EXT_CFG_INDEX_FN_SHIFT    * 12
+PCIe_RGR1_SW_INIT1             * &9210
+PCIe_RGR1_SW_INIT1_POWERDOWN   * 1:SHL:1
+PCIe_RGR1_SW_INIT1_RESET       * 1:SHL:0
 
 ; Gigabit Ethernet
 GENET_Base   *        &01580000

s/PCI

+;
+; Copyright (c) 2019, RISC OS Open Ltd
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;
+
+        GET     Hdr:ListOpts
+        GET     Hdr:CPU.Arch
+        GET     Hdr:Macros
+        GET     Hdr:Proc
+        GET     Hdr:System
+        GET     Hdr:PCI
+        GET     hdr.BCM2835
+        GET     hdr.StaticWS
+
+        IMPORT  HAL_CounterDelay
+        IMPORT  memcpy
+        EXPORT  PCI_Init
+        EXPORT  HAL_PCIReadConfigByte
+        EXPORT  HAL_PCIReadConfigHalfword
+        EXPORT  HAL_PCIReadConfigWord
+        EXPORT  HAL_PCIWriteConfigByte
+        EXPORT  HAL_PCIWriteConfigHalfword
+        EXPORT  HAL_PCIWriteConfigWord
+        EXPORT  HAL_PCISlotTable
+        EXPORT  HAL_PCIAddresses
+
+        AREA    |Asm$$Code|, CODE, READONLY, PIC
+
+; Timeouts
+PCILinkUpTries  * 1000
+PCILinkUpDelay  * 1000                  ; Microseconds
+PCIResetDelay   * 1000                  ; Microseconds
+
+; Config layout
+PCI_Init ROUT
+        CPUDetect a1
+        MOVLS   pc, lr
+
+        Push    "v1-v3,lr"
+
+        ; The PCIe registers have already been mapped in as part of PeriBase2
+        LDR     v1, PeriBase2
+        ADD     v1, v1, #PCIe_Base
+
+        ; First get into a known state in case of a soft reset
+        LDR     v2, =PCIe_RGR1_SW_INIT1
+        LDR     a1, [v1, v2]
+        ORR     a1, a1, #PCIe_RGR1_SW_INIT1_POWERDOWN :OR: PCIe_RGR1_SW_INIT1_RESET
+        STR     a1, [v1, v2]
+        MOV     a1, #PCIResetDelay
+        BL      HAL_CounterDelay
+
+        ; Power up the controller
+        LDR     a4, [v1, v2]
+        BIC     a4, a4, #PCIe_RGR1_SW_INIT1_POWERDOWN
+        STR     a4, [v1, v2]
+
+        ; Knock out the unused controller interrupts
+        MVN     a1, #0
+        LDR     a3, =PCIe_INTR2_CLEAR
+        STR     a1, [v1, a3]
+        LDR     lr, [v1, a3]            ; Flush
+        LDR     a3, =PCIe_INTR2_MASK_SET
+        STR     a1, [v1, a3]
+        LDR     lr, [v1, a3]            ; Flush
+
+        ; Bring out of reset
+        BIC     a4, a4, #PCIe_RGR1_SW_INIT1_RESET
+        STR     a4, [v1, v2]
+
+        ; Wait up to 1s for link up, we're pretty sure the VIA USB chip is there
+        LDR     v2, =PCIe_LINK_STATUS
+        MOV     v3, #PCILinkUpTries
+10
+        LDR     a1, [v1, v2]
+        AND     a1, a1, #PCIe_LINK_STATUS_PORT :OR: PCIe_LINK_STATUS_DOWNLINK_ACT :OR: PCIe_LINK_STATUS_PHYLINK_UP
+        TEQ     a1, #PCIe_LINK_STATUS_PORT :OR: PCIe_LINK_STATUS_DOWNLINK_ACT :OR: PCIe_LINK_STATUS_PHYLINK_UP
+        BEQ     %FT20
+
+        MOV     a1, #PCILinkUpDelay
+        BL      HAL_CounterDelay
+
+        SUBS    v3, v3, #1
+        BNE     %BT10
+
+        ; Oh crap, timed out, don't admit the PCI bus is present
+        Pull    "v1-v3, pc"
+20
+        ; Sanity check the built in bridge
+        LDRH    a1, [v1, #PCIe_BRIDGE_CFG + PCIConf_DeviceID]
+        MOVW    a2, #&2711              ; BCM2711
+        TEQ     a1, a2
+        LDREQH  a1, [v1, #PCIe_BRIDGE_CFG + PCIConf_VendorID]
+        MOVWEQ  a2, #&14E4              ; Broadcom
+        TEQEQ   a1, a2
+        LDREQB  a1, [v1, #PCIConf_HeaderType]
+        TEQEQ   a1, #1                  ; Bridge
+        Pull    "v1-v3, pc",NE
+
+        ; Ensure the VIA USB chip appears as bus 0/devfn 0
+        MOV     a1, #0
+        STRB    a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_PrimaryBus]
+        STRB    a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_SecondaryBus]
+        STRB    a1, [v1, #PCIe_BRIDGE_CFG + PCIConf1_SubordinateBus]
+
+      [ {FALSE}
+        ; Unlike platforms where there are sockets on the motherboard into which arbitrary
+        ; PCI cards could be plugged, there are only known devices present, so there's no need
+        ; to go probing and allocating memory space - just set up the BARs from hardcoded knowledge.
+      |
+        ! 0, "PCIe not yet configuring memory/IO windows"
+      ]
+        Pull    "v1-v3, pc"
+
+HAL_PCIWriteConfigByte ROUT
+        MOV     ip, #-1
+        B       %FT10
+HAL_PCIWriteConfigHalfword
+        MOV     ip, #-2
+        B       %FT10
+HAL_PCIWriteConfigWord
+        MOV     ip, #-4
+        B       %FT10
+HAL_PCIReadConfigByte
+        MOV     ip, #1
+        B       %FT10
+HAL_PCIReadConfigHalfword
+        MOV     ip, #2
+        B       %FT10
+HAL_PCIReadConfigWord
+        MOV     ip, #4
+10
+        CMP     a1, #1                  ; Range check the bus
+        CMPCC   a2, #256                ; Range check the 5:3 devfn
+        MVNCS   a1, #0
+        MOVCS   pc, lr
+
+      [ {FALSE}
+        ; Massage bus/devfn into index format
+        MOV     a1, a1, LSL #PCIe_EXT_CFG_INDEX_BUS_SHIFT
+        ASSERT  (PCIe_EXT_CFG_INDEX_DEV_SHIFT - PCIe_EXT_CFG_INDEX_FN_SHIFT) = 3
+        ASSERT  (PCIe_EXT_CFG_INDEX_BUS_SHIFT - PCIe_EXT_CFG_INDEX_DEV_SHIFT) = 5
+        ASSERT  PCIe_EXT_CFG_INDEX_DEV_SHIFT > PCIe_EXT_CFG_INDEX_FN_SHIFT
+        ORR     a1, a1, a2, LSL #PCIe_EXT_CFG_INDEX_FN_SHIFT
+      |
+        ; Accessing non existant bus/devfn combinations stalls for a few seconds
+        ORRS    a1, a1, a2
+        MVNNE   a1, #0
+        MOVNE   ip, ip, LSL #3
+        RSBNE   ip, ip, #32
+        MOVNE   a1, a1, LSR ip          ; Clip to byte/halfword/word
+        MOVNE   pc, lr
+      ]
+        LDR     a2, PeriBase2
+        ADD     a2, a2, #PCIe_Base
+        ADD     a2, a2, #PCIe_EXT_CFG_INDEX
+        STR     a1, [a2]
+        SUB     a2, a2, #PCIe_EXT_CFG_INDEX - PCIe_EXT_CFG_DATA
+
+        MOVS    ip, ip
+        BPL     %FT20
+
+        ; Write op
+        CMP     ip, #-2
+        STRGTB  a4, [a2, a3]
+        STREQH  a4, [a2, a3]
+        STRLT   a4, [a2, a3]
+        MOV     pc, lr
+20
+        ; Read op
+        CMP     ip, #2
+        LDRLTB  a1, [a2, a3]
+        LDREQH  a1, [a2, a3]
+        LDRGT   a1, [a2, a3]
+        MOV     pc, lr
+
+HAL_PCIAddresses ROUT
+        Push    "v1, lr"
+        CMP     a2, #7*4
+        MOVCS   a3, #7*4
+        MOVCC   a3, a2
+        MOV     v1, a3                  ; The smaller of the two
+        ADR     a2, %FT10
+        BL      memcpy
+
+        MOV     a1, v1
+        Pull    "v1, pc"
+10
+        DCD     0                       ; Memory space description
+        DCD     0
+        DCD     &1000
+        DCD     0                       ; IO space description
+        DCD     0
+        DCD     &1000
+        DCD     0                       ; Inbound RAM adjustment
+
+HAL_PCISlotTable ROUT
+        CMP     a2, #4 + 8
+        ADRCS   ip, %FT30
+        ASSERT  (%FT40 - %FT30) = 4 + 8
+        LDMCSIA ip, {a2-a4}
+        STMCSIA a1, {a2-a4}
+        MOV     a1, #4 + 8
+        MOV     pc, lr
+30
+        DCD     1                       ; Table comprising only 1 slot
+
+        DCB     0                       ; Bus
+        DCB     0*8                     ; Devno
+        DCB     255, 255, 255, 255      ; Interrupt numbers (none currently)
+        DCB     2_1111                  ; Flags
+        DCB     0                       ; Slot number for motherboard
+        ALIGN
+40
+        END

s/Top

@@ -123,6 +123,16 @@
         IMPORT  HAL_NVMemoryRead
         IMPORT  HAL_NVMemoryWrite
 
+        IMPORT  PCI_Init
+        IMPORT  HAL_PCIReadConfigByte
+        IMPORT  HAL_PCIReadConfigHalfword
+        IMPORT  HAL_PCIReadConfigWord
+        IMPORT  HAL_PCIWriteConfigByte
+        IMPORT  HAL_PCIWriteConfigHalfword
+        IMPORT  HAL_PCIWriteConfigWord
+        IMPORT  HAL_PCISlotTable
+        IMPORT  HAL_PCIAddresses
+
         IMPORT  HAL_UARTPorts
         IMPORT  HAL_UARTStartUp
         IMPORT  HAL_UARTShutdown
@@ -726,6 +736,17 @@ $table DATA
       ]
 
         NullEntry ; HAL_PCIFeatures
+      [ table_idx == 2
+        HALEntry HAL_PCIReadConfigByte
+        HALEntry HAL_PCIReadConfigHalfword
+        HALEntry HAL_PCIReadConfigWord
+        HALEntry HAL_PCIWriteConfigByte
+        HALEntry HAL_PCIWriteConfigHalfword
+        HALEntry HAL_PCIWriteConfigWord
+        NullEntry ; HAL_PCISpecialCycle
+        HALEntry HAL_PCISlotTable
+        HALEntry HAL_PCIAddresses
+      |
         NullEntry ; HAL_PCIReadConfigByte
         NullEntry ; HAL_PCIReadConfigHalfword
         NullEntry ; HAL_PCIReadConfigWord
@@ -735,6 +756,7 @@ $table DATA
         NullEntry ; HAL_PCISpecialCycle
         NullEntry ; HAL_PCISlotTable
         NullEntry ; HAL_PCIAddresses
+      ]
 
         HALEntry HAL_PlatformName
         NullEntry
@@ -904,6 +926,7 @@ HAL_Init
 50
         BL      Timer_Init
         BL      IIC_Init
+        BL      PCI_Init
 
      [ HALDebug
         BL      HAL_DebugTXStrInline
@@ -985,7 +1008,9 @@ HAL_HardwareInfo
         MOV     pc, lr
 
 HAL_PlatformInfo
-        MOV     ip, #2_10000    ; no podules,no PCI cards,no multi CPU,no soft off,and soft ROM
+        CPUDetect ip
+        MOVHI   ip, #2_10010    ; no podules, PCI cards, no multi CPU, no soft off, and soft ROM
+        MOVLS   ip, #2_10000    ; no podules, no PCI cards, no multi CPU, no soft off, and soft ROM
         STR     ip, [a2]
         MOV     ip, #2_11111    ; mask of valid bits
         STR     ip, [a3]