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On encountering an exponent > &4100 (or > &FE0000 for extended packed) to consider as a NaN or infinity, the emulation ends up in LDFConvert_Packed_NaNInf.
However, this is written as a leaf function and returns with MOV PC,LR when the singular caller of it doesn't expect a return so the LR value is actually still pointing at the last BL around line 1926. This creates an infinite loop.
Escape the loop by popping the true return value which was stacked on entry.

Version 4.38. Tagged as 'FPASC-4_38'

Return +INF and a divide by zero exception for things like 0^-0.5 principally to match what is expected by the C standard, and also so BASIC64 matches the result for 1/SQR(0) too.

These aren't needed to create the directories as
the AAsmModule make file does so.

Version 4.37. Not tagged

Spotted by nemo, change by Jon Abbot:
https://www.riscosopen.org/forum/forums/4/topics/14289

Version 4.37. Tagged as 'FPASC-4_37'

Detail:
  Makefile rewritten. All the changes elsewhere reflect the fact that
  CoreDir, VeneerDir and FileExt are now passed in from the makefile,
  since that has visibility of filespec differences between OSes.


Version 4.36. Not tagged

Detail:
  riscos/Makefile - tweak FPEAnchor handling so that 26bit RAM builds use the legacy low FPEAnchor location instead of storing FPEAnchor locally. This results in a read-only module that can be used in custom ROMs, and saves a few bytes of space.
Admin:
  Tested via building PlingSystem and checking FPEAnchorType is set correctly


Version 4.36. Tagged as 'FPASC-4_36'

Detail:
  coresrc/s/fpeundef - Fix FPEUndefHandler to make sure FPEReturn is called with Rwp pointing to the current context, not the global workspace. If the instruction which failed the condition code check was followed by one which passes the check, we'd end up trying to interpret the global workspace as a FP context, leading to unpredictable results (e.g. workspace corruption if the instruction writes to a register)
Admin:
  Tested on Raspberry Pi 3
  Fixes issue seen where "ADFLTD F1,F1,F0 : MVFS F0,F1" was corrupting the FPE context pointer due to MVFS writing to F0, causing a crash on all following FP instructions
  Also likely to fix issue reported on forums:
  https://www.riscosopen.org/forum/forums/11/topics/5265


Version 4.35. Tagged as 'FPASC-4_35'

Added options files to allow FPEmulator binaries in !System to be built using standard Machine identifiers.

Detail:
  This is necessitated by the fact that from version 4.34, we include
  Hdr:CPU.Arch to decide whether to adapt to architectural changes in ARMv5
  and ARMv7, and that header file uses the Machine build switch.

Retagged as 'FPASC-4_34'

Detail:
  Previously would abort if an untaken conditional FPA instruction was
  followed by another FPA instruction due to workspace pointer corruption.
  Re-ordered things so that this no longer happens.
Admin:
  !Draw now works on Raspberry Pi 3

Retagged as 'FPASC-4_34'

Detail:
  Untaken WFCEQ instruction on module finalisation caused undefined
  instruction to be generated during OS_Reset (e.g. Ctrl-Break).

Retagged as 'FPASC-4_34'

Detail:
  * In ARMv7 onwards, the undefined instruction processor vector can be
    entered for untaken conditional architecturally undefined instructions
    (and for these purposes, all FPA instructions can be considered
    architecturally undefined) so we now need to perform the condition code
    check in software even for the first FPA instruction in a run.
  * There were a few cases where the FPEmulator module itself does some
    untaken FPA instructions (to access a hardware FPA) before its undefined
    instruction handler is installed. These have been replaced with
    conditional branches over on the opposite condition.
  * Related bugfix: since ARMv5, the "NV" condition code space has been
    considered to represent different instruction encodings and because
    there were never any MCR2, CDP2 etc instructions for the FPA
    coprocessor, these cause the CPU to take the undefined instruction
    processor vector. But due to the nature of the previous condition code
    checks in our undefined instruction handler, an NV instruction that was
    first in a run of FPA instructions would always be executed, while one
    that was later in a run of FPA instructions would never be. This has
    now been changed so that they all generate an undefined instruction
    exception on ARMv5 onwards, wherever they are found.
Admin:
  Tested on Raspberry Pi 3.

Version 4.34. Tagged as 'FPASC-4_34'

Detail:
  Clone of Cortex-A8 target, for Cortex-A7/A15/A17.
Admin:
  Submission from Willi Theiss.
  Tagged as FPASC-4_33-1 since existing binaries unchanged.

Detail:
  The Raspberry Pi ROM now joins the IOMD ROM in supporting multiple
  architectures, in this case ARMv6 and ARMv7. This has been achieved by
  creating a new machine type specific for Raspberry Pi. The old ARM11ZF
  machine type remains for builds that are ARM11-only.

Version 4.33. Tagged as 'FPASC-4_33'

Detail:
  Code restructuring performed in FPASC-4_12 resulted in an unintentional change in behaviour on ARM2/ARM3 systems when FPEmulator attempts to pass on an abort to the next claimant of the undefined instruction vector.
  Specifically, FPEmulator's startup code was making a note of the address of the current undef environment handler, instead of the address of the pointer to the current handler. This meant that if OS_ChangeEnvironment was used to change the handler once FPEmulator had been loaded, the new handler would never get called - only the old handler would get called.
  On later systems this bug didn't occur as (a) the kernel has a veneer around the undef environment handler (instead of branching straight to the current claimant from the undef vector), and (b) OS_ClaimProcessorVector tells FPEmulator directly where to go next instead of the module having to try and guess for itself.
  File changes:
  - vensrc/riscos/start: Adjust handling of "LDR PC,xxx" undef vector so that the address being loaded from is cached instead of the contents of the address. Construct special code to use when the FPEmulator context is disabled and we want to immediately pass along the abort.
  - vensrc/riscos/globalws: Reserve workspace for storing the passalong code
Admin:
  Tested on RISC OS 3.1 under ArcEm
  ARM3 detection routines which rely on the undef environment handler now work correctly instead of failing with undefined instruction errors
  No impact on builds targeting RISC OS 3.5+ as all changes are wrapped in [ :LNOT: Arm600 ]


Version 4.32. Tagged as 'FPASC-4_32'

Comments updated in CortexA8/CortexA9/STB55/STB5cx/Tungsten.
Machine '32' offers SoftOnly now.
Removed fpemedusa and Phoebe.
Removed some proliferating !MkROM obey files.

Version 4.31. Tagged as 'FPASC-4_31'

Detail:
  Settings are cloned from Tungsten, CortexA8 and other modern machines.
Admin:
  Untested, but Adrian and John have done identical changes and they report
  success.

Version 4.30. Tagged as 'FPASC-4_30'

Detail:
  This is just a clone of the CortexA8 file.
Admin:
  Submission from Willi Theiß.
  Retagged as 'FPASC-4_29' since other builds are unaffected.

Detail:
  Unlike most modules which can just store the zero page pointers in their workspace, FPEmulator is a bit trickier since the zero page pointers are needed from within abort handlers and other places where the module workspace pointer is hard to come by (in fact, FPEmulator uses FPEAnchor to store the module workspace pointer)
  So rather than break/rework lots of perfectly good code, there are now three different FPEmulator builds available, selected via the new FPEAnchorType option:
  * FPEAnchorType=Low will select a build suitable for machines with FPEAnchor at its original location in zero page. This is the default for ROM builds.
  * FPEAnchorType=High will select a build suitable for the FPEAnchor location (&ffff0ff4) that's used with zero page relocation. Machines with relocated zero page must specify this option in their components file.
  * FPEAnchorType=Local will select a build suitable for softloading. Rather than rely on using a zero page location for storing the workspace pointer, the module just stores it within itself. This option is selected automatically for RAM builds and can't be overriden via the components file.
  File changes:
  riscos/Makefile - Reworked makefile to support the new options
  riscos/FPEMacros - Updated AdrWS macro to work with FPEAnchorType=Local
  riscos/options - For non-local builds, declare the appropriate value for FPEAnchor
  riscos/start - Use appropriate FPEAnchor initialisation code
Admin:
  All 3 configs tested (ROM builds on BB-xM, RAM softload on Iyonix)


Version 4.29. Tagged as 'FPASC-4_29'

Detail:
  riscos/s/CortexA8 - Made a copy of the Tungsten FPASC config file for use with Cortex/OMAP ROM builds
Admin:
  Tested on rev C2 beagleboard.
  Not tagged - no functional changes.


Version 4.28. Not tagged

Detail:
  Emulation of instructions like LDFD were doing writeback to r13 with
  interrupts disabled but then re-enabling interrupts before actually
  reading memory, thereby leaving a window for an interrupt to be handled and
  corrupt the unprotected stack memory below r13.
  Fixes ROOL ticket #225.
Admin:
  Changes originally by mwuerthner and committed by srevill on 2009-12-04.

Tagged as 'FPASC-4_28'

Detail:
  Broke certain denormalised cases of multiply, divide and remainder.
  Problem originally reported on Iyonix discussion group (failed Paranoia tesst).
Admin:
  Changes originally committed by kbracey on 2004-09-21.

Tagged as 'FPASC-4_23'

Detail:
  * Denormalised numbers now held consistently in their nominal precision.
    MVF/MNF/ABS of a denormalised number without a change of precision
    treated specially, much like signalling NaNs. This prevents spurious
    underflow traps if they're enabled. Previously

         ; Underflow traps on
         LDFS    F0,DenormalisedSingle
         MVFS    F0,F0

    or

         ; Underflow traps off
         LDFD    F0,SmallestNormalDouble
         MUFD    F0,F0,#0.5
         ; Turn underflow traps on
         STFD    F0,xxx

    would have generated traps.

  * LDFP/STFP rearrangement of NaN significands reinstated, as DDT
    can now make use of it.

  * Typos in over/underflow code for LDFP corrected.

  * Experimental dynamic rounding controls added to FPSR (for emulator
    only). Currently disabled; does not affect LDFP or STFP yet.

Admin:
  Changes originally committed by kbracey on 2004-01-26.

Tagged as 'FPASC-4_21'

Detail:
  * Bug fix in STFP - minor error at bottom of word.
  * New switch to allow use of CLZ.
Admin:
  Changes originally committed by kbracey on 2003-02-21.

Tagged as 'FPASC-4_20'

Detail:
  * Generated NaNs were always negative - they were supposed to have a sign
    based on the operands. As a side effect, some internal routines were not
    obeying their advertised API - this has been corrected.
  * Generated NaNs no longer contained a reason code - this was a deliberate
    ARM change, but I'm going to have a philosophical disagreement and reverse
    it.
Admin:
  Changes originally committed by kbracey on 2002-03-04.

Tagged as 'FPASC-4_18'

Detail:
  Added check to make sure we ignore undefined instruction exceptions generated
  while in Thumb state.
Admin:
  Changes originally committed by kbracey on 2001-05-31.
  This fix was originally applied to an earlier version of ARM's code and has
  been rebased at ARM's version 1.13 for licensing reasons.
  However, since this was the last change before ARM version 1.13 was merged
  into the RISC OS source tree (on 2001-07-25), it is also representative of
  the the RISC OS sources at that date, barring licence header differences.

Tagged as 'Thumb-fix' and 'FPASC-4_16'

Detail:
  ARMv4 architecture (e.g. StrongARM) gains UMULL instruction which enables
  faster calculations at the expense of ARM 2/3/6/7 compatibility.
Admin:
  Changes originally by kbracey, committed 1998-03-27 by mstphens.
  This fix was originally applied to an earlier version of ARM's code and has
  been rebased at ARM's version 1.13 for licensing reasons.

Tagged as 'UMULL-fix'

Detail:
  These had a silicon bug in STM^ instructions - enable workaround by defining
  SASTMhatbroken.
Admin:
  This fix was originally applied to an earlier version of ARM's code and has
  been rebased at ARM's version 1.13 for licensing reasons.

Tagged as 'StrongARM-fix'

This is version 1.13. The original distribution archive is in doc/fpe400.zip.
The coresrc subdirectory is the only part of the official distribution used
in the RISC OS implementation, and is rearranged to use a "s" subdirectory
rather than a ".s" suffix as is customary for RISC OS builds.

Detail:
  This change fixes ticket #225 (post-indexed LDFD via r13 sometimes reading
  corrupted values).

Version 4.28. Tagged as 'FPASC-4_28'

Detail:
  Machine=32 is now built so that it doesn't use UMULL. This is because we
  now require it to operate on ARMv3 Risc PCs and A7000(+).
Admin:
  Untested, but should be low risk.

Version 4.27. Tagged as 'FPASC-4_27'

Detail:
Admin:


Version 4.26. Tagged as 'FPASC-4_26'

Version 4.25. Tagged as 'FPASC-4_25'

(already replaced by Tungsten and Phoebe).

Version 4.24. Tagged as 'FPASC-4_24'

Detail:
  Exports VersionNum to BBE.
  Also removed dynamic dependencies fom Makefile.
Admin:
  Tested in a Tungsten BBE build.

Retagged, since this won't affect existing builds.

Fixed an error in "UseCLZ" case (ie thus affecting only Iyonix currently), which broke certain denormalised cases of multiply, divide and remainder.

Problem originally reported on Iyonix discussion group (failed Paranoia tesst).

Version 4.23. Tagged as 'FPASC-4_23'

Retagged as 'FPASC-4_22'

Detail:
  Files modified: riscos.Makefile, MkRom310, MkRom350, MkRom, MkRomIyx
  Files added: riscos.MkRom380, MkRomUrs
               s.Phoebe, STB5, Tungsten
Admin:
  Upated from Kev's machine by Mike H.

Version 4.22. Tagged as 'FPASC-4_22'

Detail:
  doc.*
Admin:
  From Kev's machine.

  MVF/MNF/ABS of a denormalised number without a change of precision
  treated specially, much like signalling NaNs. This prevents spurious
  underflow traps if they're enabled. Previously

       ; Underflow traps on
       LDFS    F0,DenormalisedSingle
       MVFS    F0,F0

  or

       ; Underflow traps off
       LDFD    F0,SmallestNormalDouble
       MUFD    F0,F0,#0.5
       ; Turn underflow traps on
       STFD    F0,xxx

  would have generated traps.

* LDFP/STFP rearrangement of NaN significands reinstated, as DDT
  can now make use of it.

* Typos in over/underflow code for LDFP corrected.

* Makefile changed to build in rm.${SYSTEM} instead of rm.${MACHINE}.

* Experimental dynamic rounding controls added to FPSR (for emulator
  only). Currently disabled; does not affect LDFP or STFP yet.

Version 4.21. Tagged as 'FPASC-4_21'