1. 29 Feb, 2016 2 commits
    • Ben Avison's avatar
      Another tweak for ARMv8 compatibility · 8e7c29ab
      Ben Avison authored
      Detail:
        Untaken WFCEQ instruction on module finalisation caused undefined
        instruction to be generated during OS_Reset (e.g. Ctrl-Break).
      
      Retagged as 'FPASC-4_34'
      8e7c29ab
    • Ben Avison's avatar
      Support ARMv8 (and potentially some ARMv7) cores, and a bugfix. · 8377f0c4
      Ben Avison authored
      Detail:
        * In ARMv7 onwards, the undefined instruction processor vector can be
          entered for untaken conditional architecturally undefined instructions
          (and for these purposes, all FPA instructions can be considered
          architecturally undefined) so we now need to perform the condition code
          check in software even for the first FPA instruction in a run.
        * There were a few cases where the FPEmulator module itself does some
          untaken FPA instructions (to access a hardware FPA) before its undefined
          instruction handler is installed. These have been replaced with
          conditional branches over on the opposite condition.
        * Related bugfix: since ARMv5, the "NV" condition code space has been
          considered to represent different instruction encodings and because
          there were never any MCR2, CDP2 etc instructions for the FPA
          coprocessor, these cause the CPU to take the undefined instruction
          processor vector. But due to the nature of the previous condition code
          checks in our undefined instruction handler, an NV instruction that was
          first in a run of FPA instructions would always be executed, while one
          that was later in a run of FPA instructions would never be. This has
          now been changed so that they all generate an undefined instruction
          exception on ARMv5 onwards, wherever they are found.
      Admin:
        Tested on Raspberry Pi 3.
      
      Version 4.34. Tagged as 'FPASC-4_34'
      8377f0c4
  2. 04 Nov, 2015 1 commit
    • ROOL's avatar
      Extra target · be163f25
      ROOL authored
      Detail:
        Clone of Cortex-A8 target, for Cortex-A7/A15/A17.
      Admin:
        Submission from Willi Theiss.
        Tagged as FPASC-4_33-1 since existing binaries unchanged.
      be163f25
  3. 02 Feb, 2015 1 commit
    • Ben Avison's avatar
      Add Raspberry Pi 2 support · d5049d39
      Ben Avison authored
      Detail:
        The Raspberry Pi ROM now joins the IOMD ROM in supporting multiple
        architectures, in this case ARMv6 and ARMv7. This has been achieved by
        creating a new machine type specific for Raspberry Pi. The old ARM11ZF
        machine type remains for builds that are ARM11-only.
      
      Version 4.33. Tagged as 'FPASC-4_33'
      d5049d39
  4. 31 May, 2013 1 commit
    • Jeffrey Lee's avatar
      Fix interaction with undefined instruction environment handler in pre-RISC OS 3.5 builds · da6e0a95
      Jeffrey Lee authored
      Detail:
        Code restructuring performed in FPASC-4_12 resulted in an unintentional change in behaviour on ARM2/ARM3 systems when FPEmulator attempts to pass on an abort to the next claimant of the undefined instruction vector.
        Specifically, FPEmulator's startup code was making a note of the address of the current undef environment handler, instead of the address of the pointer to the current handler. This meant that if OS_ChangeEnvironment was used to change the handler once FPEmulator had been loaded, the new handler would never get called - only the old handler would get called.
        On later systems this bug didn't occur as (a) the kernel has a veneer around the undef environment handler (instead of branching straight to the current claimant from the undef vector), and (b) OS_ClaimProcessorVector tells FPEmulator directly where to go next instead of the module having to try and guess for itself.
        File changes:
        - vensrc/riscos/start: Adjust handling of "LDR PC,xxx" undef vector so that the address being loaded from is cached instead of the contents of the address. Construct special code to use when the FPEmulator context is disabled and we want to immediately pass along the abort.
        - vensrc/riscos/globalws: Reserve workspace for storing the passalong code
      Admin:
        Tested on RISC OS 3.1 under ArcEm
        ARM3 detection routines which rely on the undef environment handler now work correctly instead of failing with undefined instruction errors
        No impact on builds targeting RISC OS 3.5+ as all changes are wrapped in [ :LNOT: Arm600 ]
      
      
      Version 4.32. Tagged as 'FPASC-4_32'
      da6e0a95
  5. 27 Jan, 2013 1 commit
    • Robert Sprowson's avatar
      IOMD moved to distinct machine · 2ddd6e61
      Robert Sprowson authored
      Comments updated in CortexA8/CortexA9/STB55/STB5cx/Tungsten.
      Machine '32' offers SoftOnly now.
      Removed fpemedusa and Phoebe.
      Removed some proliferating !MkROM obey files.
      
      Version 4.31. Tagged as 'FPASC-4_31'
      2ddd6e61
  6. 10 May, 2012 1 commit
  7. 02 Jan, 2012 1 commit
  8. 12 Sep, 2011 1 commit
  9. 06 Aug, 2011 1 commit
    • Jeffrey Lee's avatar
      Update to work with zero page relocation · 19a98c14
      Jeffrey Lee authored
      Detail:
        Unlike most modules which can just store the zero page pointers in their workspace, FPEmulator is a bit trickier since the zero page pointers are needed from within abort handlers and other places where the module workspace pointer is hard to come by (in fact, FPEmulator uses FPEAnchor to store the module workspace pointer)
        So rather than break/rework lots of perfectly good code, there are now three different FPEmulator builds available, selected via the new FPEAnchorType option:
        * FPEAnchorType=Low will select a build suitable for machines with FPEAnchor at its original location in zero page. This is the default for ROM builds.
        * FPEAnchorType=High will select a build suitable for the FPEAnchor location (&ffff0ff4) that's used with zero page relocation. Machines with relocated zero page must specify this option in their components file.
        * FPEAnchorType=Local will select a build suitable for softloading. Rather than rely on using a zero page location for storing the workspace pointer, the module just stores it within itself. This option is selected automatically for RAM builds and can't be overriden via the components file.
        File changes:
        riscos/Makefile - Reworked makefile to support the new options
        riscos/FPEMacros - Updated AdrWS macro to work with FPEAnchorType=Local
        riscos/options - For non-local builds, declare the appropriate value for FPEAnchor
        riscos/start - Use appropriate FPEAnchor initialisation code
      Admin:
        All 3 configs tested (ROM builds on BB-xM, RAM softload on Iyonix)
      
      
      Version 4.29. Tagged as 'FPASC-4_29'
      19a98c14
  10. 23 Jun, 2010 1 commit
  11. 22 May, 2010 7 commits
    • Ben Avison's avatar
      Fix interrupt hole on post-indexed load from r13 in non-USR modes · 1d182c17
      Ben Avison authored
      Detail:
        Emulation of instructions like LDFD were doing writeback to r13 with
        interrupts disabled but then re-enabling interrupts before actually
        reading memory, thereby leaving a window for an interrupt to be handled and
        corrupt the unprotected stack memory below r13.
        Fixes ROOL ticket #225.
      Admin:
        Changes originally by mwuerthner and committed by srevill on 2009-12-04.
      
      Tagged as 'FPASC-4_28'
      1d182c17
    • Ben Avison's avatar
      Fixed an error in "UseCLZ" case · 7da0e8cd
      Ben Avison authored
      Detail:
        Broke certain denormalised cases of multiply, divide and remainder.
        Problem originally reported on Iyonix discussion group (failed Paranoia tesst).
      Admin:
        Changes originally committed by kbracey on 2004-09-21.
      
      Tagged as 'FPASC-4_23'
      7da0e8cd
    • Ben Avison's avatar
      Multiple fixes · 9d4798d6
      Ben Avison authored
      Detail:
        * Denormalised numbers now held consistently in their nominal precision.
          MVF/MNF/ABS of a denormalised number without a change of precision
          treated specially, much like signalling NaNs. This prevents spurious
          underflow traps if they're enabled. Previously
      
               ; Underflow traps on
               LDFS    F0,DenormalisedSingle
               MVFS    F0,F0
      
          or
      
               ; Underflow traps off
               LDFD    F0,SmallestNormalDouble
               MUFD    F0,F0,#0.5
               ; Turn underflow traps on
               STFD    F0,xxx
      
          would have generated traps.
      
        * LDFP/STFP rearrangement of NaN significands reinstated, as DDT
          can now make use of it.
      
        * Typos in over/underflow code for LDFP corrected.
      
        * Experimental dynamic rounding controls added to FPSR (for emulator
          only). Currently disabled; does not affect LDFP or STFP yet.
      
      Admin:
        Changes originally committed by kbracey on 2004-01-26.
      
      Tagged as 'FPASC-4_21'
      9d4798d6
    • Ben Avison's avatar
      Bug fix, and optimisation for XScale · dce7dc2f
      Ben Avison authored
      Detail:
        * Bug fix in STFP - minor error at bottom of word.
        * New switch to allow use of CLZ.
      Admin:
        Changes originally committed by kbracey on 2003-02-21.
      
      Tagged as 'FPASC-4_20'
      dce7dc2f
    • Ben Avison's avatar
      Two changes to Generated NaN handling in ARM's core · 294e81b9
      Ben Avison authored
      Detail:
        * Generated NaNs were always negative - they were supposed to have a sign
          based on the operands. As a side effect, some internal routines were not
          obeying their advertised API - this has been corrected.
        * Generated NaNs no longer contained a reason code - this was a deliberate
          ARM change, but I'm going to have a philosophical disagreement and reverse
          it.
      Admin:
        Changes originally committed by kbracey on 2002-03-04.
      
      Tagged as 'FPASC-4_18'
      294e81b9
    • Ben Avison's avatar
      Support for processors which feature Thumb mode. · 50bb8c9f
      Ben Avison authored
      Detail:
        Added check to make sure we ignore undefined instruction exceptions generated
        while in Thumb state.
      Admin:
        Changes originally committed by kbracey on 2001-05-31.
        This fix was originally applied to an earlier version of ARM's code and has
        been rebased at ARM's version 1.13 for licensing reasons.
        However, since this was the last change before ARM version 1.13 was merged
        into the RISC OS source tree (on 2001-07-25), it is also representative of
        the the RISC OS sources at that date, barring licence header differences.
      
      Tagged as 'Thumb-fix' and 'FPASC-4_16'
      50bb8c9f
    • Ben Avison's avatar
      Add Use64bitMultiply option. · b7f7d326
      Ben Avison authored
      Detail:
        ARMv4 architecture (e.g. StrongARM) gains UMULL instruction which enables
        faster calculations at the expense of ARM 2/3/6/7 compatibility.
      Admin:
        Changes originally by kbracey, committed 1998-03-27 by mstphens.
        This fix was originally applied to an earlier version of ARM's code and has
        been rebased at ARM's version 1.13 for licensing reasons.
      
      Tagged as 'UMULL-fix'
      b7f7d326
  12. 21 May, 2010 2 commits
    • Ben Avison's avatar
      Workaround for pre-rev 3 SA110 chips. · 3b620adc
      Ben Avison authored
      Detail:
        These had a silicon bug in STM^ instructions - enable workaround by defining
        SASTMhatbroken.
      Admin:
        This fix was originally applied to an earlier version of ARM's code and has
        been rebased at ARM's version 1.13 for licensing reasons.
      
      Tagged as 'StrongARM-fix'
      3b620adc
    • Ben Avison's avatar
      Initial import on a vendor branch for ARM's BSD-licenced releases of the FPASC. · 827b1609
      Ben Avison authored
      This is version 1.13. The original distribution archive is in doc/fpe400.zip.
      The coresrc subdirectory is the only part of the official distribution used
      in the RISC OS implementation, and is rearranged to use a "s" subdirectory
      rather than a ".s" suffix as is customary for RISC OS builds.
      827b1609
  13. 04 Dec, 2009 1 commit
  14. 30 Apr, 2009 1 commit
    • Ben Avison's avatar
      Change to build options. · c3137b50
      Ben Avison authored
      Detail:
        Machine=32 is now built so that it doesn't use UMULL. This is because we
        now require it to operate on ARMv3 Risc PCs and A7000(+).
      Admin:
        Untested, but should be low risk.
      
      Version 4.27. Tagged as 'FPASC-4_27'
      c3137b50
  15. 19 Jun, 2006 1 commit
  16. 16 Mar, 2005 1 commit
  17. 25 Jan, 2005 1 commit
  18. 12 Nov, 2004 1 commit
    • Ben Avison's avatar
      BBE tidying. · 2b27010d
      Ben Avison authored
      Detail:
        Exports VersionNum to BBE.
        Also removed dynamic dependencies fom Makefile.
      Admin:
        Tested in a Tungsten BBE build.
      
      Retagged, since this won't affect existing builds.
      2b27010d
  19. 21 Sep, 2004 1 commit
  20. 02 Jul, 2004 1 commit
  21. 20 Jun, 2004 2 commits
  22. 26 Jan, 2004 1 commit
    • Kevin Bracey's avatar
      * Denormalised numbers now held consistently in their nominal precision. · ce61b80e
      Kevin Bracey authored
        MVF/MNF/ABS of a denormalised number without a change of precision
        treated specially, much like signalling NaNs. This prevents spurious
        underflow traps if they're enabled. Previously
      
             ; Underflow traps on
             LDFS    F0,DenormalisedSingle
             MVFS    F0,F0
      
        or
      
             ; Underflow traps off
             LDFD    F0,SmallestNormalDouble
             MUFD    F0,F0,#0.5
             ; Turn underflow traps on
             STFD    F0,xxx
      
        would have generated traps.
      
      * LDFP/STFP rearrangement of NaN significands reinstated, as DDT
        can now make use of it.
      
      * Typos in over/underflow code for LDFP corrected.
      
      * Makefile changed to build in rm.${SYSTEM} instead of rm.${MACHINE}.
      
      * Experimental dynamic rounding controls added to FPSR (for emulator
        only). Currently disabled; does not affect LDFP or STFP yet.
      
      Version 4.21. Tagged as 'FPASC-4_21'
      ce61b80e
  23. 21 Feb, 2003 1 commit
  24. 12 Apr, 2002 1 commit
    • Steve Revill's avatar
      * Fixed install phase; · 928be59e
      Steve Revill authored
        * Moved stripdepnd out of Makefile;
        * Variants passed on amu command line.
      Detail:
        * You can now specify the precise build variant of the FPEmulator by passing
          System=... and FPE_APCS=... on the amu command line. There are now more
          files in riscos.s to set the options for various types (as per Wimp).
          The default FPE as was is now built with: System="RO380" FPE_APCS="3/32bit"
      Admin:
        Builds.
      Version 4.19. Tagged as 'FPASC-4_19'
      928be59e
  25. 04 Mar, 2002 1 commit
    • Kevin Bracey's avatar
      Two changes to ARM's version 1.17 core: · 8f2c3a3e
      Kevin Bracey authored
      * Generated NaNs were always negative - they were supposed to have a sign
        based on the operands. As a side effect, some internal routines were not
        obeying their advertised API - this has been corrected.
      * Generated NaNs no longer contained a reason code - this was a deliberate
        ARM change, but I'm going to have a philosophical disagreement and reverse
        it.
      
      Version 4.18. Tagged as 'FPASC-4_18'
      8f2c3a3e
  26. 31 Aug, 2001 2 commits
  27. 25 Jul, 2001 1 commit
  28. 31 May, 2001 1 commit
  29. 02 Oct, 2000 1 commit
  30. 24 Mar, 2000 1 commit
    • Kevin Bracey's avatar
      Fixed error in multiply routine reported by RISC OS Ltd. · aa5adf86
      Kevin Bracey authored
      Detail:
        When the long multiply option was added on the Ursula branch, an inexplicable
        change to a single instruction in the original non-long multiply code
        appeared.
        Result would have been slightly inaccurate multiplies when both operands
        had more than 32 bits of mantissa.
        Original code restored.
      
      Version 4.13. Tagged as 'FPASC-4_13'
      aa5adf86