Added a CPU-independent version of CLZ that I wrote last year, plus equivalent...

Added a CPU-independent version of CLZ that I wrote last year, plus equivalent functions for trailing zeroes and leading and trailing ones.

Version 0.10. Tagged as 'AsmUtils-0_10'

Makefile

@@ -78,13 +78,13 @@ SOURCE     =
 EXPORTS    = 
 
 OBJS=   o.callbacks o.sixtyfour o.heapswis o.rminfo o.irqs \
-        o.osvarlen o.muldiv o.modulefp o.fpsr o.escape
+        o.osvarlen o.muldiv o.modulefp o.fpsr o.escape o.clz
 
 OBJSZ=  oz.callbacks oz.sixtyfour oz.heapswis oz.rminfo oz.irqs \
-        oz.osvarlen oz.muldiv oz.modulefp oz.fpsr oz.escape
+        oz.osvarlen oz.muldiv oz.modulefp oz.fpsr oz.escape oz.clz
 
 HDRS=   h.callbacks h.sixtyfour h.heapswis h.rminfo h.irqs \
-        h.osvarlen h.muldiv h.modulefp h.fpsr h.escape
+        h.osvarlen h.muldiv h.modulefp h.fpsr h.escape h.clz
 
 LIBS = ${TARGET} ${TARGETZ}
 
@@ -130,6 +130,7 @@ export_hdrs: ${HDRS} export_dirs
 	${CP} h.modulefp   ${LIBDIR}.h.modulefp  ${CPFLAGS}
 	${CP} h.fpsr       ${LIBDIR}.h.fpsr      ${CPFLAGS}
 	${CP} h.escape     ${LIBDIR}.h.escape    ${CPFLAGS}
+	${CP} h.clz        ${LIBDIR}.h.clz       ${CPFLAGS}
 	${CP} VersionNum   ${LIBDIR}.LibVersion  ${CPFLAGS}
 	@echo ${COMPONENT}: export complete (hdrs)
 

VersionNum

-/* (0.09)
+/* (0.10)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
+ * Last processed by srccommit version: 1.2.
  *
  */
-#define Module_MajorVersion_CMHG        0.09
+#define Module_MajorVersion_CMHG        0.10
 #define Module_MinorVersion_CMHG
-#define Module_Date_CMHG                04 Jun 2000
+#define Module_Date_CMHG                01 Jul 2005
 
-#define Module_MajorVersion             "0.09"
-#define Module_Version                  9
+#define Module_MajorVersion             "0.10"
+#define Module_Version                  10
 #define Module_MinorVersion             ""
-#define Module_Date                     "04 Jun 2000"
+#define Module_Date                     "01 Jul 2005"
 
-#define Module_FullVersion              "0.09"
+#define Module_ApplicationDate          "01-Jul-05"
+
+#define Module_ComponentName            "AsmUtils"
+#define Module_ComponentPath            "RiscOS/Sources/Lib/AsmUtils"
+
+#define Module_FullVersion              "0.10"
+#define Module_HelpVersion              "0.10 (01 Jul 2005)"
+#define Module_LibraryVersionInfo       "0:10"

h/clz

+/* Copyright 2005 Castle Technology Ltd
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*
+ *  AsmUtils (clz.h)
+ *
+ * Copyright (C) 2004 Castle Technology Ltd
+ *
+ * Author: Ben Avison
+ *
+ */
+
+#ifndef asmuntils_clz_h_included
+#define asmuntils_clz_h_included
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* These functions are designed for CPUs without the CLZ instruction */
+
+extern unsigned int clz(unsigned int);
+  /* Returns the number of leading zero bits in the argument, 0 ... 32 */
+
+extern unsigned int ctz(unsigned int);
+  /* Returns the number of trailing zero bits in the argument, 0 ... 32 */
+
+extern unsigned int clo(unsigned int);
+  /* Returns the number of leading one bits in the argument, 0 ... 32 */
+
+extern unsigned int cto(unsigned int);
+  /* Returns the number of trailing one bits in the argument, 0 ... 32 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

s/clz

+; Copyright 2005 Castle Technology Ltd
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+; Count leading/trailing zeros/ones without using the CLZ instruction
+; Copyright (C) 2004 Castle Technology Ltd
+; Author: Ben Avison
+
+        GET     Hdr:ListOpts
+        GET     Hdr:Macros
+        GET     Hdr:APCS.<APCS>
+
+        AREA    |Asm$$Code|, CODE, READONLY
+
+        EXPORT  |clz|
+        EXPORT  |ctz|
+        EXPORT  |clo|
+        EXPORT  |cto|
+
+|clz|
+        ORRS    a4, a1, a1, LSR #1
+        MOVEQ   a1, #32
+        ORRNE   a1, a4, a4, LSR #2
+        Return  , LinkNotStacked, EQ
+        ORR     a1, a1, a1, LSR #4
+        LDR     a2, =&06C9C57D
+        ORR     a1, a1, a1, LSR #8
+        ADR     a3, table
+        ORR     a1, a1, a1, LSR #16
+        MLAS    a1, a2, a1, a2
+        LDRNEB  a1, [a3, a1, LSR #27]
+        Return  , LinkNotStacked
+
+|ctz|
+        SUBS    a4, a1, #1
+        MOVCC   a1, #32
+        Return  , LinkNotStacked, CC
+        LDR     a2, =&06C9C57D
+        BIC     a1, a1, a4
+        MUL     a1, a2, a1
+        ADR     a3, table
+        LDRB    a1, [a3, a1, LSR #27]
+        RSB     a1, a1, #32
+        Return  , LinkNotStacked
+
+|clo|
+        ANDS    a4, a1, a1, ASR #1
+        MOVPL   a1, #0
+        ANDMI   a1, a4, a4, ASR #2
+        Return  , LinkNotStacked, PL
+        AND     a1, a1, a1, ASR #4
+        LDR     a2, =&06C9C57D
+        AND     a1, a1, a1, ASR #8
+        ADR     a3, table
+        AND     a1, a1, a1, ASR #16
+        RSB     a1, a1, #0
+        MUL     a1, a2, a1
+        LDRB    a1, [a3, a1, LSR #27]
+        Return  , LinkNotStacked
+
+|cto|
+        ADDS    a4, a1, #1
+        MOVEQ   a1, #32
+        Return  , LinkNotStacked, EQ
+        LDR     a2, =&06C9C57D
+        BIC     a1, a4, a1
+        MUL     a1, a2, a1
+        ADR     a3, table
+        LDRB    a1, [a3, a1, LSR #27]
+        RSB     a1, a1, #32
+        Return  , LinkNotStacked
+
+table
+        = 32, 31, 14, 30, 22, 13, 29, 19,  2, 21, 12, 10, 25, 28, 18,  8
+        =  1, 15, 23, 20,  3, 11, 26,  9, 16, 24,  4, 27, 17,  5,  6,  7
+
+        END