Commit cf66486f authored by Timothy E Baldwin's avatar Timothy E Baldwin Committed by ROOL

Use standard register name

Change register name from `lk` to `lr`.


Version 5.15. Not tagged
parent 9eb077b4
/* (5.15)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 5.15
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 08 May 2015
#define Module_Date_CMHG 25 Jul 2020
#define Module_MajorVersion "5.15"
#define Module_Version 515
#define Module_MinorVersion ""
#define Module_Date "08 May 2015"
#define Module_Date "25 Jul 2020"
#define Module_ApplicationDate "08-May-15"
#define Module_ApplicationDate "25-Jul-20"
#define Module_ComponentName "xpand"
#define Module_ComponentPath "castle/RiscOS/Tools/Sources/xpand"
#define Module_FullVersion "5.15"
#define Module_HelpVersion "5.15 (08 May 2015)"
#define Module_HelpVersion "5.15 (25 Jul 2020)"
#define Module_LibraryVersionInfo "5:15"
......@@ -17,7 +17,7 @@
; This makes it possible to call code which scribbles on all the
; registers with a standard ARM procedure call, e.g. from C.
;
; If the code called also scribbles on lk, you must regain control
; If the code called also scribbles on lr, you must regain control
; by forcing it to branch to asmcall_exit.
;
; NB it relies on scribbling on memory addressed pc-relative, so it
......@@ -30,7 +30,7 @@ r2 RN 2
r3 RN 3
r4 RN 4
ip RN 12
lk RN 14
lr RN 14
pc RN 15
AREA |C$$code|, CODE, READONLY
......@@ -44,17 +44,17 @@ asmcall_call
; r1, r2, r3: parameters for it
ADR ip, asmcall_savedregs
STMIA ip, {r4-lk}
STMIA ip, {r4-lr}
MOV ip, r0
MOV r0, r1
MOV r1, r2
MOV r2, r3
MOV lk, pc
MOV lr, pc
MOV pc, ip
asmcall_exit
NOP ; 2 spurious instructions here in case the caller
NOP ; forgets to allow for prefetch ...
ADR ip, asmcall_savedregs
LDMIA ip, {r4-lk}
MOV pc, lk
LDMIA ip, {r4-lr}
MOV pc, lr
END
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