Commit ac8f2a6d authored by Ben Avison's avatar Ben Avison

Support for OMAP543x, AM5728 and ADFS 4

Detail:
  * Complete the Cortex-A7 support which was initially added for RPi 2, to
    allow for builds that only target Cortex-A7. Because Cortex-A15 and
    Cortex-A17 CPUs are indistinguishable architecturally from Cortex-A7
    (all are ARMv7VE with VFPv4, Advanced SIMD v2 and hardware integer divide)
    any such platforms are expected to use Machine=CortexA7. Also bear in
    mind that if we ever support multiple cores on big.LITTLE CPUs, execution
    can move between these core types at runtime, making an assembly time
    option to distinguish between them meaningless!
  * Correct Machines All and All32 to include support for VFPv4
  * Decloak the ATA driver SWI chunk
  * Add a global error allocation for use by the ATA subsystem (placed in
    global space because it propagates into the CD stack)


Version 2.55. Tagged as 'HdrSrc-2_55'
parent 2aa15909
/* (2.54)
/* (2.55)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.54
#define Module_MajorVersion_CMHG 2.55
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Sep 2015
#define Module_Date_CMHG 08 Nov 2015
#define Module_MajorVersion "2.54"
#define Module_Version 254
#define Module_MajorVersion "2.55"
#define Module_Version 255
#define Module_MinorVersion ""
#define Module_Date "29 Sep 2015"
#define Module_Date "08 Nov 2015"
#define Module_ApplicationDate "29-Sep-15"
#define Module_ApplicationDate "08-Nov-15"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.54"
#define Module_HelpVersion "2.54 (29 Sep 2015)"
#define Module_LibraryVersionInfo "2:54"
#define Module_FullVersion "2.55"
#define Module_HelpVersion "2.55 (08 Nov 2015)"
#define Module_LibraryVersionInfo "2:55"
......@@ -200,7 +200,7 @@ MchFlg_VH * 2_00000000000010000000000000000000
MchFlg_Vv4 * 2_00000000000100000000000000000000
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
MchFlg_A * 2_00000000001000000000000000000000
MchFlg_A * 2_00000000001000000000000000000000
; Remaining flags reserved for future use
;MchFlg_ * 2_00000000010000000000000000000000
;MchFlg_ * 2_00000000100000000000000000000000
......@@ -455,20 +455,23 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
|
[ "$Machine" = "CortexA9" ; Cortex A9
[ "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
ArchitectureOption v7_VFP3D32H_SIMD
|
[ "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "All" ; if the target code is required to run on
; any RISC OS machine
ArchitectureOption v2
ArchitectureOption v2a_FPA
ArchitectureOption v7_VFP3D32H_SIMD
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "All32" ; if the target code is required to run on
; any 32-bit capable RISC OS machine
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v7_VFP3D32H_SIMD
ArchitectureOption v7_VFP4D32_SIMD
|
! 1, "Unrecognised machine: $Machine"
]
......@@ -481,6 +484,7 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
]
]
]
]
]
GBLL SupportARMv3
......
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Cortex-A7/-A15/-A17 machine: ARMv7VE + VFPv4 + NEON
GBLS Machine
Machine SETS "CortexA7"
GET Hdr:Machine.Machine
END
......@@ -57,6 +57,7 @@ M_STB400 SETL Machine="STB400"
GBLL M_RPi
GBLL M_CortexA8
GBLL M_CortexA9
GBLL M_CortexA7
GBLL M_IOMD
GBLL M_STB5
GBLL M_Tungsten
......@@ -68,9 +69,13 @@ M_ARM11ZF SETL Machine="ARM11ZF"
M_RPi SETL Machine="RPi"
M_CortexA8 SETL Machine="CortexA8"
M_CortexA9 SETL Machine="CortexA9"
M_CortexA7 SETL Machine="CortexA7"
M_IOMD SETL Machine="IOMD"
M_STB5 SETL Machine="STB5"
M_Tungsten SETL Machine="Tungsten"
[ Machine="CortexA15" :LOR: Machine="CortexA17"
! 1, "You probably wanted to use Machine=CortexA7"
]
; Are we only supporting 26bit processor modes?
; If true, we mustn't rely on MSR, MRS etc, and we should be
......@@ -80,7 +85,7 @@ No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega
; Are we only supporting 32bit processor modes?
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; If this makes your head hurt, the other way of looking at it is
; 26/32 neutral => No32bitCode FALSE No26bitCode FALSE
......@@ -91,7 +96,7 @@ No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR:
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug
......@@ -129,7 +134,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -173,7 +178,7 @@ DontUseVCO SETL M_Lazarus :LOR: M_STB400
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; General flag for STB/NCD-type products
GBLL STB
......@@ -202,7 +207,7 @@ MaxI2Cspeed SETA 100
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 :LOR: M_CortexA7
; Support for network 'podule' cards
GBLL NetPodSupport
......
......@@ -663,6 +663,7 @@ ErrorBase_Econet * &300
AddError BadCommandOption, "Bad command option"
AddError UnknownSerialOp, "Unknown serial operation"
AddError BadHard, "BadHard" ; "Unsupported hardware configuration"
AddError TooComplex, "TooComplex:Transfer too complex"
; International errors
......
......@@ -1733,6 +1733,11 @@ RTCSWI EQU &00001653
RTCSWI_Base EQU &000594C0
RTCSWI_Name SETS "RTC"
GBLS ATASwitchSWI_Name
ATASwitchSWI EQU &0000165E
ATASwitchSWI_Base EQU &00059780
ATASwitchSWI_Name SETS "ATA"
GBLS SPIDriverSWI_Name
SPIDriverSWI EQU &00001662
SPIDriverSWI_Base EQU &00059880
......
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