Commit 9f9d0319 authored by Ben Avison's avatar Ben Avison

New compile-time architecture flags:

  * ARMv7VE (virtualisation extension)
  * ARMv8
  * ARMv8 cryptographic extension
  Machine=RPi builds now targets ARMv8 as well as ARMv6 and ARMv7;
  Machine=CortexA7 builds now set the VE flag; and All and All32 include ARMv8.

Version 2.58. Tagged as 'HdrSrc-2_58'
parent 1e044546
/* (2.57)
/* (2.58)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.57
#define Module_MajorVersion_CMHG 2.58
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 29 Nov 2015
#define Module_Date_CMHG 29 Feb 2016
#define Module_MajorVersion "2.57"
#define Module_Version 257
#define Module_MajorVersion "2.58"
#define Module_Version 258
#define Module_MinorVersion ""
#define Module_Date "29 Nov 2015"
#define Module_Date "29 Feb 2016"
#define Module_ApplicationDate "29-Nov-15"
#define Module_ApplicationDate "29-Feb-16"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.57"
#define Module_HelpVersion "2.57 (29 Nov 2015)"
#define Module_LibraryVersionInfo "2:57"
#define Module_FullVersion "2.58"
#define Module_HelpVersion "2.58 (29 Feb 2016)"
#define Module_LibraryVersionInfo "2:58"
......@@ -161,51 +161,53 @@ MchFlg_v5 * 2_00000000000000000000000000000100
MchFlg_v6 * 2_00000000000000000000000000001000
; DBG, DMB, PLI, PLDW and ThumbEE instruction set
MchFlg_v7 * 2_00000000000000000000000000010000
; CRC32, HLT, LDA(EX), SEVL, STL(EX), VMAXNM, VMINNM, VRINT, VSEL
MchFlg_v8 * 2_00000000000000000000000000100000
; SWP and SWPB
MchFlg_a * 2_00000000000000000000000000100000
MchFlg_a * 2_00000000000000000000000001000000
; Hardware FPA - FPA10 if v2 (ARM3); FPA11 if v3 (ARM700 or ARM7500FE)
MchFlg_F * 2_00000000000000000000000001000000
MchFlg_F * 2_00000000000000000000000010000000
; Withdrawal of 26-bit modes
MchFlg_G * 2_00000000000000000000000010000000
MchFlg_G * 2_00000000000000000000000100000000
; 64+32x32 bit MLA and MUL
MchFlg_M * 2_00000000000000000000000100000000
MchFlg_M * 2_00000000000000000000001000000000
; BX and Thumb - Thumbv1 if ARMv4; Thumbv2 if ARMv5; Thumbv3 if ARMv6
; no established terminology for later revisions
MchFlg_T * 2_00000000000000000000001000000000
MchFlg_T * 2_00000000000000000000010000000000
; Enhanced DSP extension - 32+16*16, 33+32*16, 64+16*16 MLA and MUL,
; saturated ADD/SUB
MchFlg_E * 2_00000000000000000000010000000000
MchFlg_E * 2_00000000000000000000100000000000
; PLD, LDRD/STRD, MRRC/MCRR
MchFlg_P * 2_00000000000000000000100000000000
MchFlg_P * 2_00000000000000000001000000000000
; Intel XScale extensions - 40+32*32, 40+16*16, 40+16*16+16*16 MLA,
; mini data cache
MchFlg_X * 2_00000000000000000001000000000000
MchFlg_X * 2_00000000000000000010000000000000
; Jazelle extension - BXJ
MchFlg_J * 2_00000000000000000010000000000000
MchFlg_J * 2_00000000000000000100000000000000
; Multiprocessing extensions - CLREX, YIELD, WFE, WFI, SEV, SMI and
; security extensions
MchFlg_K * 2_00000000000000000100000000000000
MchFlg_K * 2_00000000000000001000000000000000
; Thumb 2 and more - MOVW, MOVH, bitfield operations, DSB, ISB,
; 8/16/64 bit LDR/STREX, LDRT/STRT for halfwords and signed bytes, 32-32*32 MLS
MchFlg_T2 * 2_00000000000000001000000000000000
MchFlg_T2 * 2_00000000000000010000000000000000
; Virtualisation extension - ERET, HVC, banked MRS and MSR and hardware divide
MchFlg_VE * 2_00000000000000100000000000000000
; Cryptographic extension - AES, SHA1, SHA256
MchFlg_C * 2_00000000000001000000000000000000
; VFP - VFPv1 if ARMv5T; VFPv2 if ARMv5TE or ARMv6; VFPv3 if ARMv7
MchFlg_V * 2_00000000000000010000000000000000
MchFlg_V * 2_00000000000010000000000000000000
; VFP D variant (double precision)
MchFlg_VD * 2_00000000000000100000000000000000
MchFlg_VD * 2_00000000000100000000000000000000
; VFP 32 double-precision registers variant
MchFlg_V32 * 2_00000000000001000000000000000000
MchFlg_V32 * 2_00000000001000000000000000000000
; VFP half-precision variant
MchFlg_VH * 2_00000000000010000000000000000000
MchFlg_VH * 2_00000000010000000000000000000000
; VFPv4 - fused multiply-accumulate
MchFlg_Vv4 * 2_00000000000100000000000000000000
MchFlg_Vv4 * 2_00000000100000000000000000000000
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
MchFlg_A * 2_00000000001000000000000000000000
MchFlg_A * 2_00000010000000000000000000000000
; Remaining flags reserved for future use
;MchFlg_ * 2_00000000010000000000000000000000
;MchFlg_ * 2_00000000100000000000000000000000
;MchFlg_ * 2_00000001000000000000000000000000
;MchFlg_ * 2_00000010000000000000000000000000
;MchFlg_ * 2_00000100000000000000000000000000
;MchFlg_ * 2_00001000000000000000000000000000
;MchFlg_ * 2_00010000000000000000000000000000
......@@ -221,6 +223,7 @@ MchFlgs_v5T * MchFlgs_v4T :OR: MchFlg_v5
MchFlgs_v5TE * MchFlgs_v5T :OR: MchFlg_E :OR: MchFlg_P
MchFlgs_v6 * MchFlgs_v5TE :OR: MchFlg_v6 :OR: MchFlg_J
MchFlgs_v7 * MchFlgs_v6 :OR: MchFlg_v7 :OR: MchFlg_K :OR: MchFlg_T2
MchFlgs_v8 * (MchFlgs_v7 :AND: :NOT: MchFlg_a) :OR: MchFlg_v8 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
GBLA MchFlgs_Cumulative
MchFlgs_Cumulative SETA 0
......@@ -368,8 +371,11 @@ MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
[ "$arch" = "v7_VFP3D32H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
|
[ "$arch" = "v7_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
[ "$arch" = "v7VE_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
|
[ "$arch" = "v8"
MchFlgs SETA MchFlgs_v8
|
! 1, "Unrecognised architecture: $arch"
]
......@@ -419,6 +425,7 @@ MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg
]
]
]
]
MchFlgs_Cumulative SETA MchFlgs_Cumulative :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
MEND
......@@ -445,12 +452,13 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D
|
[ "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle two architectures
[ "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
ArchitectureOption v6K_VFP2D
ArchitectureOption v7_VFP4D32_SIMD
ArchitectureOption v7VE_VFP4D32_SIMD
ArchitectureOption v8
|
[ "$Machine" = "CortexA7" ; Cortex A7
ArchitectureOption v7_VFP4D32_SIMD
ArchitectureOption v7VE_VFP4D32_SIMD
|
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
......@@ -465,13 +473,13 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
; any RISC OS machine
ArchitectureOption v2
ArchitectureOption v2a_FPA
ArchitectureOption v7_VFP4D32_SIMD
ArchitectureOption v8
|
[ "$Machine" = "All32" ; if the target code is required to run on
; any 32-bit capable RISC OS machine
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v7_VFP4D32_SIMD
ArchitectureOption v8
|
! 1, "Unrecognised machine: $Machine"
]
......@@ -512,6 +520,11 @@ SupportARMv7 SETL (MchFlgs_Cumulative :AND: MchFlg_v7) > 0
GBLL NoARMv7
NoARMv7 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_v7) > 0
GBLL SupportARMv8
SupportARMv8 SETL (MchFlgs_Cumulative :AND: MchFlg_v8) > 0
GBLL NoARMv8
NoARMv8 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_v8) > 0
GBLL SupportARMa
SupportARMa SETL (MchFlgs_Cumulative :AND: MchFlg_a) > 0
GBLL NoARMa
......@@ -567,6 +580,16 @@ SupportARMT2 SETL (MchFlgs_Cumulative :AND: MchFlg_T2) > 0
GBLL NoARMT2
NoARMT2 SETL (MchFlgs_CumulativeNOT :AND: MchFlg_T2) > 0
GBLL SupportARMVE
SupportARMVE SETL (MchFlgs_Cumulative :AND: MchFlg_VE) > 0
GBLL NoARMVE
NoARMVE SETL (MchFlgs_CumulativeNOT :AND: MchFlg_VE) > 0
GBLL SupportARMC
SupportARMC SETL (MchFlgs_Cumulative :AND: MchFlg_C) > 0
GBLL NoARMC
NoARMC SETL (MchFlgs_CumulativeNOT :AND: MchFlg_C) > 0
GBLL SupportARMV
SupportARMV SETL (MchFlgs_Cumulative :AND: MchFlg_V) > 0
GBLL NoARMV
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment