Commit 993162c8 authored by Robert Sprowson's avatar Robert Sprowson Committed by ROOL

Suppress macro name conflicts

ObjAsm 4.08 spots macros using MyBase$Suffix where MyBase is a substring of another macro. Generic32 has CL$op and SE$op which causes many hundreds of warnings due to CLRV and SETV for example.
Write out the macros longhand, and use a longer unique name for the generic implementation.

Version 2.91. Tagged as 'HdrSrc-2_91'
parent 61adf0db
/* (2.90)
/* (2.91)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 2.90
#define Module_MajorVersion_CMHG 2.91
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 20 May 2020
#define Module_Date_CMHG 25 Jul 2020
#define Module_MajorVersion "2.90"
#define Module_Version 290
#define Module_MajorVersion "2.91"
#define Module_Version 291
#define Module_MinorVersion ""
#define Module_Date "20 May 2020"
#define Module_Date "25 Jul 2020"
#define Module_ApplicationDate "20-May-20"
#define Module_ApplicationDate "25-Jul-20"
#define Module_ComponentName "HdrSrc"
#define Module_FullVersion "2.90"
#define Module_HelpVersion "2.90 (20 May 2020)"
#define Module_LibraryVersionInfo "2:90"
#define Module_FullVersion "2.91"
#define Module_HelpVersion "2.91 (25 Jul 2020)"
#define Module_LibraryVersionInfo "2:91"
......@@ -764,7 +764,8 @@ ctl SETL psr:RIGHT:4 = "_all" :LOR: psr:RIGHT:3 = "psr" :LOR: psr:RIGHT:4
; * Except for the T bit (assumed to be 0), only the indicated PSR fields will be touched (e.g. NZCV always preserved)
; * They assemble down to one instruction (CPS or MRS) wherever possible
; * Due to the limits of CPS this means they're all unconditional
; * For the one-instruction MRS form you'll have to provide 'hints' for the current mode/IF bits. But even though you're specifying the mode + interrupt flags, these macros are still better than WritePSRc (for ARMv6+)
; * For the one-instruction MRS form you'll have to provide 'hints' for the current mode/IF bits. But even though
; you're specifying the mode + interrupt flags, these macros are still better than WritePSRc (for ARMv6+)
; * When building 26/32bit neutral or 26bit-only versions:
; * The saved PSR will be the CPSR if MRS supported, else it's a saved PC (same rules as SavePSR, WritePSRc, etc.)
; * The SetMode macros will preserve the 32bit-ness of the host, unless asked to switch into a 32bit-only mode (e.g. SYS)
......@@ -824,7 +825,20 @@ ctl SETL psr:RIGHT:4 = "_all" :LOR: psr:RIGHT:3 = "psr" :LOR: psr:RIGHT:4
; *** required, or no $mode provided. ***
; *************************************************
MACRO
SE$op $mode, $regtmp, $oldpsr
SEI $mode, $regtmp, $oldpsr
internalSEI $mode, $regtmp, $oldpsr
MEND
MACRO
SEF $mode, $regtmp, $oldpsr
internalSEF $mode, $regtmp, $oldpsr
MEND
MACRO
SEIF $mode, $regtmp, $oldpsr
internalSEIF $mode, $regtmp, $oldpsr
MEND
MACRO
internalSE$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
......@@ -852,7 +866,20 @@ CPU32_bits IFto32 $op
; *** required, or no $mode provided. ***
; *************************************************
MACRO
CL$op $mode, $regtmp, $oldpsr
CLI $mode, $regtmp, $oldpsr
internalCLI $mode, $regtmp, $oldpsr
MEND
MACRO
CLF $mode, $regtmp, $oldpsr
internalCLF $mode, $regtmp, $oldpsr
MEND
MACRO
CLIF $mode, $regtmp, $oldpsr
internalCLIF $mode, $regtmp, $oldpsr
MEND
MACRO
internalCL$op $mode, $regtmp, $oldpsr
CPU32_bits IFto32 $op
[ :LNOT: NoARMv6
[ "$oldpsr" <> ""
......
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