Commit 89b7f37b authored by Ben Avison's avatar Ben Avison

Add Raspberry Pi 2 support

Detail:
  The Raspberry Pi ROM now joins the IOMD ROM in supporting multiple
  architectures, in this case ARMv6 and ARMv7. This has been achieved by
  creating a new machine type specific for Raspberry Pi. The old ARM11ZF
  machine type remains for builds that are ARM11-only.

  The Raspberry Pi 2 uses the Cortex-A7 processor, which includes version 4
  of the VFP instruction set and version 2 of the Advanced SIMD (NEON)
  instruction set. You can now switch on this at assembly time using the new
  switches NoARMVv4 and SupportARMVv4.

Version 2.50. Tagged as 'HdrSrc-2_50'
parent 2145199f
/* (2.49)
/* (2.50)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.49
#define Module_MajorVersion_CMHG 2.50
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 06 Jan 2015
#define Module_Date_CMHG 02 Feb 2015
#define Module_MajorVersion "2.49"
#define Module_Version 249
#define Module_MajorVersion "2.50"
#define Module_Version 250
#define Module_MinorVersion ""
#define Module_Date "06 Jan 2015"
#define Module_Date "02 Feb 2015"
#define Module_ApplicationDate "06-Jan-15"
#define Module_ApplicationDate "02-Feb-15"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.49"
#define Module_HelpVersion "2.49 (06 Jan 2015)"
#define Module_LibraryVersionInfo "2:49"
#define Module_FullVersion "2.50"
#define Module_HelpVersion "2.50 (02 Feb 2015)"
#define Module_LibraryVersionInfo "2:50"
......@@ -196,11 +196,12 @@ MchFlg_VD * 2_00000000000000100000000000000000
MchFlg_V32 * 2_00000000000001000000000000000000
; VFP half-precision variant
MchFlg_VH * 2_00000000000010000000000000000000
; VFPv4 - fused multiply-accumulate
MchFlg_Vv4 * 2_00000000000100000000000000000000
; Advanced SIMD extensions - integer only if no VFP; FP half or single
; precision options mirror the VFP options
MchFlg_A * 2_00000000000100000000000000000000
MchFlg_A * 2_00000000001000000000000000000000
; Remaining flags reserved for future use
;MchFlg_ * 2_00000000001000000000000000000000
;MchFlg_ * 2_00000000010000000000000000000000
;MchFlg_ * 2_00000000100000000000000000000000
;MchFlg_ * 2_00000001000000000000000000000000
......@@ -366,6 +367,9 @@ MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
|
[ "$arch" = "v7_VFP3D32H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
|
[ "$arch" = "v7_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
|
! 1, "Unrecognised architecture: $arch"
]
......@@ -414,6 +418,7 @@ MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg
]
]
]
]
MchFlgs_Cumulative SETA MchFlgs_Cumulative :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
MEND
......@@ -440,6 +445,13 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D
|
[ "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle two architectures
ArchitectureOption v6K_VFP2D
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "CortexA7" ; Cortex A7
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD
|
......@@ -467,6 +479,8 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
]
]
]
]
]
]
GBLL SupportARMv3
......@@ -569,6 +583,11 @@ SupportARMVH SETL (MchFlgs_Cumulative :AND: MchFlg_VH) > 0
GBLL NoARMVH
NoARMVH SETL (MchFlgs_CumulativeNOT :AND: MchFlg_VH) > 0
GBLL SupportARMVv4
SupportARMVH SETL (MchFlgs_Cumulative :AND: MchFlg_Vv4) > 0
GBLL NoARMVv4
NoARMVH SETL (MchFlgs_CumulativeNOT :AND: MchFlg_Vv4) > 0
GBLL SupportARMA
SupportARMA SETL (MchFlgs_Cumulative :AND: MchFlg_A) > 0
GBLL NoARMA
......
......@@ -54,6 +54,7 @@ M_STB400 SETL Machine="STB400"
GBLL M_All32
GBLL M_Archimedes
GBLL M_ARM11ZF
GBLL M_RPi
GBLL M_CortexA8
GBLL M_CortexA9
GBLL M_IOMD
......@@ -64,6 +65,7 @@ M_All SETL Machine="All"
M_All32 SETL Machine="All32"
M_Archimedes SETL Machine="Archimedes"
M_ARM11ZF SETL Machine="ARM11ZF"
M_RPi SETL Machine="RPi"
M_CortexA8 SETL Machine="CortexA8"
M_CortexA9 SETL Machine="CortexA9"
M_IOMD SETL Machine="IOMD"
......@@ -78,7 +80,7 @@ No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega
; Are we only supporting 32bit processor modes?
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
; If this makes your head hurt, the other way of looking at it is
; 26/32 neutral => No32bitCode FALSE No26bitCode FALSE
......@@ -89,7 +91,7 @@ No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR:
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF :LOR: M_CortexA9
NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug
......@@ -127,7 +129,7 @@ MEMC_Type SETS "IOMD"
GetMEMC SETS "GET Hdr:IO." :CC: MEMC_Type
GBLS MEMM_Type
[ M_CortexA8 :LOR: M_CortexA9 :LOR: M_ARM11ZF
[ M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
MEMM_Type SETS "VMSAv6"
|
MEMM_Type SETS "ARM600"
......@@ -171,7 +173,7 @@ DontUseVCO SETL M_Lazarus :LOR: M_STB400
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
HAL SETL M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
; General flag for STB/NCD-type products
GBLL STB
......@@ -200,7 +202,7 @@ MaxI2Cspeed SETA 100
; E2ROM is supported at i2c addresses >= A8 in addition to normal CMOS RAM
; Note that this also controls HAL NVRAM support, and RTCSupport.
GBLL E2ROMSupport
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
E2ROMSupport SETL M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Lazarus :LOR: M_32 :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
; Support for network 'podule' cards
GBLL NetPodSupport
......@@ -246,11 +248,11 @@ MorrisSupport SETL {TRUE}
; Less blocky teletext font
GBLL HiResTTX
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi
; Teletext rendered at 8bpp
GBLL TTX256
TTX256 SETL M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF
TTX256 SETL M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_RPi
; Safe area when doing TV modes
; Expressed as percentage of screen not to use - left, bottom, right, top
......
; Copyright 2015 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Support either architecture v6Z with VFPv2 or architecture 7-A with VFPv4 and NEONv2
GBLS Machine
Machine SETS "RPi"
GET Hdr:Machine.Machine
END
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