Commit 7d0f8d91 authored by Jeffrey Lee's avatar Jeffrey Lee

Add new "26" machine type. Simplify ARM2 support.

Detail:
  hdr/Machine/26, hdr/Machine/Machine - Add new "26" machine type, which targets all 26 bit machines/OS versions (running only in 26 bit mode)
  hdr/CPU/Arch - Use ELIF to avoid bracket spam. Remove duplicate CortexA7 case.
  hdr/CPU/Generic26 - Add NOPs to PSR manipulation macros in order to make them ARM2-safe (Generic32 macros are already structured to have suitable NOPs when generating 32bit-neutral code, so it makes sense for Generic26 to take care of ARM2 as well). This removes the need for components which use these macros to insert any manual NOPs, whether for the StrongARM MSR bug or the ARM2 TEQP bug.
  hdr/CPU/Generic32 - Flag the StrongARM MSR NOP diagnostic message as a warning, so the line number can be included in the output, so developers can more easily investigate the issue.
Admin:
  Tested with PlingSystem build


Version 2.63. Tagged as 'HdrSrc-2_63'
parent 03e4d645
/* (2.62) /* (2.63)
* *
* This file is automatically maintained by srccommit, do not edit manually. * This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1. * Last processed by srccommit version: 1.1.
* *
*/ */
#define Module_MajorVersion_CMHG 2.62 #define Module_MajorVersion_CMHG 2.63
#define Module_MinorVersion_CMHG #define Module_MinorVersion_CMHG
#define Module_Date_CMHG 10 May 2016 #define Module_Date_CMHG 28 May 2016
#define Module_MajorVersion "2.62" #define Module_MajorVersion "2.63"
#define Module_Version 262 #define Module_Version 263
#define Module_MinorVersion "" #define Module_MinorVersion ""
#define Module_Date "10 May 2016" #define Module_Date "28 May 2016"
#define Module_ApplicationDate "10-May-16" #define Module_ApplicationDate "28-May-16"
#define Module_ComponentName "HdrSrc" #define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc" #define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.62" #define Module_FullVersion "2.63"
#define Module_HelpVersion "2.62 (10 May 2016)" #define Module_HelpVersion "2.63 (28 May 2016)"
#define Module_LibraryVersionInfo "2:62" #define Module_LibraryVersionInfo "2:63"
...@@ -235,197 +235,103 @@ $lab ArchitectureOption $arch ...@@ -235,197 +235,103 @@ $lab ArchitectureOption $arch
LCLA MchFlgs LCLA MchFlgs
[ "$arch" = "v2" [ "$arch" = "v2"
MchFlgs SETA 0 MchFlgs SETA 0
| ELIF "$arch" = "v2a"
[ "$arch" = "v2a"
MchFlgs SETA MchFlg_a MchFlgs SETA MchFlg_a
| ELIF "$arch" = "v2a_FPA"
[ "$arch" = "v2a_FPA"
MchFlgs SETA MchFlg_a :OR: MchFlg_F MchFlgs SETA MchFlg_a :OR: MchFlg_F
| ELIF "$arch" = "v3"
[ "$arch" = "v3"
MchFlgs SETA MchFlgs_v3 MchFlgs SETA MchFlgs_v3
| ELIF "$arch" = "v3_FPA"
[ "$arch" = "v3_FPA"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_F MchFlgs SETA MchFlgs_v3 :OR: MchFlg_F
| ELIF "$arch" = "v3G"
[ "$arch" = "v3G"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_G MchFlgs SETA MchFlgs_v3 :OR: MchFlg_G
| ELIF "$arch" = "v3M"
[ "$arch" = "v3M"
MchFlgs SETA MchFlgs_v3 :OR: MchFlg_M MchFlgs SETA MchFlgs_v3 :OR: MchFlg_M
| ELIF "$arch" = "v4xM"
[ "$arch" = "v4xM"
MchFlgs SETA MchFlgs_v4 :AND: :NOT: MchFlg_M MchFlgs SETA MchFlgs_v4 :AND: :NOT: MchFlg_M
| ELIF "$arch" = "v4"
[ "$arch" = "v4"
MchFlgs SETA MchFlgs_v4 MchFlgs SETA MchFlgs_v4
| ELIF "$arch" = "v4TxM"
[ "$arch" = "v4TxM"
MchFlgs SETA MchFlgs_v4T :AND: :NOT: MchFlg_M MchFlgs SETA MchFlgs_v4T :AND: :NOT: MchFlg_M
| ELIF "$arch" = "v4T"
[ "$arch" = "v4T"
MchFlgs SETA MchFlgs_v4T MchFlgs SETA MchFlgs_v4T
| ELIF "$arch" = "v5xM"
[ "$arch" = "v5xM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: (MchFlg_M :OR: MchFlg_T) MchFlgs SETA MchFlgs_v5T :AND: :NOT: (MchFlg_M :OR: MchFlg_T)
| ELIF "$arch" = "v5"
[ "$arch" = "v5"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_T MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_T
| ELIF "$arch" = "v5TxM"
[ "$arch" = "v5TxM"
MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_M MchFlgs SETA MchFlgs_v5T :AND: :NOT: MchFlg_M
| ELIF "$arch" = "v5T"
[ "$arch" = "v5T"
MchFlgs SETA MchFlgs_v5T MchFlgs SETA MchFlgs_v5T
| ELIF "$arch" = "v5T_VFP1"
[ "$arch" = "v5T_VFP1"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V
| ELIF "$arch" = "v5T_VFP1D"
[ "$arch" = "v5T_VFP1D"
MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v5T :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v5TExP"
[ "$arch" = "v5TExP"
MchFlgs SETA MchFlgs_v5TE :AND: :NOT: MchFlg_P MchFlgs SETA MchFlgs_v5TE :AND: :NOT: MchFlg_P
| ELIF "$arch" = "v5TE"
[ "$arch" = "v5TE"
MchFlgs SETA MchFlgs_v5TE MchFlgs SETA MchFlgs_v5TE
| ELIF "$arch" = "v5TEX"
[ "$arch" = "v5TEX"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_X MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_X
| ELIF "$arch" = "v5TE_VFP2"
[ "$arch" = "v5TE_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V
| ELIF "$arch" = "v5TE_VFP2D"
[ "$arch" = "v5TE_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v5TEJ"
[ "$arch" = "v5TEJ"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J
| ELIF "$arch" = "v5TEJ_VFP2"
[ "$arch" = "v5TEJ_VFP2"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V
| ELIF "$arch" = "v5TEJ_VFP2D"
[ "$arch" = "v5TEJ_VFP2D"
MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v5TE :OR: MchFlg_J :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v6"
[ "$arch" = "v6"
MchFlgs SETA MchFlgs_v6 MchFlgs SETA MchFlgs_v6
| ELIF "$arch" = "v6_VFP2"
[ "$arch" = "v6_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V
| ELIF "$arch" = "v6_VFP2D"
[ "$arch" = "v6_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v6 :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v6K"
[ "$arch" = "v6K"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K
| ELIF "$arch" = "v6K_VFP2"
[ "$arch" = "v6K_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V
| ELIF "$arch" = "v6K_VFP2D"
[ "$arch" = "v6K_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v6 :OR: MchFlg_K :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v6T2"
[ "$arch" = "v6T2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2
| ELIF "$arch" = "v6T2_VFP2"
[ "$arch" = "v6T2_VFP2"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V
| ELIF "$arch" = "v6T2_VFP2D"
[ "$arch" = "v6T2_VFP2D"
MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v6 :OR: MchFlg_T2 :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v7"
[ "$arch" = "v7"
MchFlgs SETA MchFlgs_v7 MchFlgs SETA MchFlgs_v7
| ELIF "$arch" = "v7_VFP3"
[ "$arch" = "v7_VFP3"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V
| ELIF "$arch" = "v7_VFP3D"
[ "$arch" = "v7_VFP3D"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD
| ELIF "$arch" = "v7_VFP3D32"
[ "$arch" = "v7_VFP3D32"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32
| ELIF "$arch" = "v7_VFP3H"
[ "$arch" = "v7_VFP3H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH
| ELIF "$arch" = "v7_VFP3DH"
[ "$arch" = "v7_VFP3DH"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_VH MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_VH
| ELIF "$arch" = "v7_VFP3D32H"
[ "$arch" = "v7_VFP3D32H"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH
| ELIF "$arch" = "v7_SIMD"
[ "$arch" = "v7_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_A
| ELIF "$arch" = "v7_VFP3_SIMD"
[ "$arch" = "v7_VFP3_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_A
| ELIF "$arch" = "v7_VFP3D32_SIMD"
[ "$arch" = "v7_VFP3D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_A
| ELIF "$arch" = "v7_VFP3H_SIMD"
[ "$arch" = "v7_VFP3H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VH :OR: MchFlg_A
| ELIF "$arch" = "v7_VFP3D32H_SIMD"
[ "$arch" = "v7_VFP3D32H_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_A
| ELIF "$arch" = "v7VE_VFP4D32_SIMD"
[ "$arch" = "v7VE_VFP4D32_SIMD"
MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A MchFlgs SETA MchFlgs_v7 :OR: MchFlg_VE :OR: MchFlg_V :OR: MchFlg_VD :OR: MchFlg_V32 :OR: MchFlg_VH :OR: MchFlg_Vv4 :OR: MchFlg_A
| ELIF "$arch" = "v8"
[ "$arch" = "v8"
MchFlgs SETA MchFlgs_v8 MchFlgs SETA MchFlgs_v8
| |
! 1, "Unrecognised architecture: $arch" ! 1, "Unrecognised architecture: $arch"
] ]
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MchFlgs_Cumulative SETA MchFlgs_Cumulative :OR: MchFlgs MchFlgs_Cumulative SETA MchFlgs_Cumulative :OR: MchFlgs
MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
MEND MEND
...@@ -434,65 +340,48 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs ...@@ -434,65 +340,48 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
ArchitectureOption v2 ArchitectureOption v2
ArchitectureOption v2a ArchitectureOption v2a
ArchitectureOption v2a_FPA ArchitectureOption v2a_FPA
| ELIF "$Machine" = "26" ; All 26-bit capable machines, running in 26-bit mode
[ "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports) ArchitectureOption v2
ArchitectureOption v2a
ArchitectureOption v2a_FPA
ArchitectureOption v3
ArchitectureOption v3_FPA
ArchitectureOption v4
ELIF "$Machine" = "32" ; basic 32-bit capable machines (used for many ARM7TDMI and ARM9 ports)
ArchitectureOption v3 ArchitectureOption v3
ArchitectureOption v3_FPA ArchitectureOption v3_FPA
ArchitectureOption v4 ArchitectureOption v4
ArchitectureOption v4T ArchitectureOption v4T
| ELIF "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
[ "$Machine" = "IOMD" ; 32-bit IOMD-class machines ARM6/ARM7/StrongARM
ArchitectureOption v3 ArchitectureOption v3
ArchitectureOption v3_FPA ArchitectureOption v3_FPA
ArchitectureOption v4 ArchitectureOption v4
| ELIF "$Machine" = "Tungsten" ; Iyonix PC
[ "$Machine" = "Tungsten" ; Iyonix PC
ArchitectureOption v5TEX ArchitectureOption v5TEX
| ELIF "$Machine" = "ARM11ZF"
[ "$Machine" = "ARM11ZF"
ArchitectureOption v6K_VFP2D ArchitectureOption v6K_VFP2D
| ELIF "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
[ "$Machine" = "RPi" ; Raspberry Pi versions are similar enough that one ROM can handle three architectures
ArchitectureOption v6K_VFP2D ArchitectureOption v6K_VFP2D
ArchitectureOption v7VE_VFP4D32_SIMD ArchitectureOption v7VE_VFP4D32_SIMD
ArchitectureOption v8 ArchitectureOption v8
| ELIF "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
[ "$Machine" = "CortexA7" ; Cortex A7
ArchitectureOption v7VE_VFP4D32_SIMD ArchitectureOption v7VE_VFP4D32_SIMD
| ELIF "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
[ "$Machine" = "CortexA8" ; Cortex A8, e.g. TI OMAP35xx
ArchitectureOption v7_VFP3D32_SIMD ArchitectureOption v7_VFP3D32_SIMD
| ELIF "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
[ "$Machine" = "CortexA9" ; Cortex A9, e.g. TI OMAP44xx, Freescale i.MX6
ArchitectureOption v7_VFP3D32H_SIMD ArchitectureOption v7_VFP3D32H_SIMD
| ELIF "$Machine" = "All" ; if the target code is required to run on
[ "$Machine" = "CortexA7" ; Cortex A7, A15 or A17, e.g. BCM2836, TI OMAP543x, TI AM5728
ArchitectureOption v7_VFP4D32_SIMD
|
[ "$Machine" = "All" ; if the target code is required to run on
; any RISC OS machine ; any RISC OS machine
ArchitectureOption v2 ArchitectureOption v2
ArchitectureOption v2a_FPA ArchitectureOption v2a_FPA
ArchitectureOption v8 ArchitectureOption v8
| ELIF "$Machine" = "All32" ; if the target code is required to run on
[ "$Machine" = "All32" ; if the target code is required to run on
; any 32-bit capable RISC OS machine ; any 32-bit capable RISC OS machine
ArchitectureOption v3 ArchitectureOption v3
ArchitectureOption v3_FPA ArchitectureOption v3_FPA
ArchitectureOption v8 ArchitectureOption v8
| |
! 1, "Unrecognised machine: $Machine" ! 1, "Unrecognised machine: $Machine"
]
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] ]
GBLL SupportARMv3 GBLL SupportARMv3
......
...@@ -334,6 +334,11 @@ $label RestPSR $reg, $cond, $fields ...@@ -334,6 +334,11 @@ $label RestPSR $reg, $cond, $fields
! 0, "Unpredictable behaviour due to deprecated RestPSR fields parameter" ! 0, "Unpredictable behaviour due to deprecated RestPSR fields parameter"
] ]
$label TEQ$cond.P pc, $reg $label TEQ$cond.P pc, $reg
[ NoARMa :LAND: "$fields"<>"f"
; Assume mode may be changing, emit NOP for ARM2
! 0, "RestPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND MEND
; **************************************************** ; ****************************************************
...@@ -361,6 +366,10 @@ $label ...@@ -361,6 +366,10 @@ $label
MOV$cond $srcreg, pc MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr) ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr TEQ$cond.P $regtmp, #$clr
]
[ NoARMa :LAND: ((($set) :OR: ($clr)) :AND: M_bits) <> 0
! 0, "SCPSR inserting NOP for ARM2 TEQP bug", 1
NOP
] ]
MEND MEND
...@@ -387,6 +396,10 @@ srcreg SETS "$oldpsr" ...@@ -387,6 +396,10 @@ srcreg SETS "$oldpsr"
$label MOV$cond $srcreg, pc $label MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #$bits ORR$cond $regtmp, $srcreg, #$bits
TEQ$cond.P $regtmp, #0 TEQ$cond.P $regtmp, #0
[ NoARMa :LAND: (($bits) :AND: M_bits) <> 0
! 0, "SETPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND MEND
; ************************************************** ; **************************************************
...@@ -411,6 +424,10 @@ srcreg SETS "$oldpsr" ...@@ -411,6 +424,10 @@ srcreg SETS "$oldpsr"
] ]
$label MOV$cond $srcreg, pc $label MOV$cond $srcreg, pc
TEQ$cond.P $srcreg, #$bits TEQ$cond.P $srcreg, #$bits
[ NoARMa :LAND: (($bits) :AND: M_bits) <> 0
! 0, "TOGPSR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND MEND
; *********************************************** ; ***********************************************
...@@ -425,6 +442,10 @@ $label MOV$cond $oldpsr, pc ...@@ -425,6 +442,10 @@ $label MOV$cond $oldpsr, pc
| |
$label TEQ$cond.P $regtog, pc $label TEQ$cond.P $regtog, pc
] ]
[ NoARMa
! 0, "TOGPSRR inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND MEND
; ************************************************* ; *************************************************
...@@ -441,10 +462,15 @@ $label WritePSRc $value, $regtmp, $cond, $oldpsr ...@@ -441,10 +462,15 @@ $label WritePSRc $value, $regtmp, $cond, $oldpsr
[ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0 [ ($value :AND::NOT: (I_bit+F_bit+SVC_mode)) <> 0
! 1, "Illegal flags for WritePSRc" ! 1, "Illegal flags for WritePSRc"
] ]
$label
[ "$oldpsr" <> "" [ "$oldpsr" <> ""
SavePSR $oldpsr, $cond SavePSR $oldpsr, $cond
] ]
$label TEQ$cond.P PC, #$value TEQ$cond.P PC, #$value
[ NoARMa
! 0, "WritePSRc inserting NOP for ARM2 TEQP bug", 1
NOP
]
MEND MEND
] ; No32bitCode ] ; No32bitCode
......
...@@ -887,7 +887,7 @@ op SETA ($op2a) :OR: (0:SHL:25) ...@@ -887,7 +887,7 @@ op SETA ($op2a) :OR: (0:SHL:25)
DCI Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype DCI Cond_$cond :OR: 2_00000001001000001111000000000000 :OR: op :OR: psrtype
[ StrongARM_MSR_bug :LAND: "$sabug" <> "safe" :LAND: "$cond" <> "AL" :LAND: "$cond" <> "" :LAND: ((psrtype :AND: &410000) = &10000) [ StrongARM_MSR_bug :LAND: "$sabug" <> "safe" :LAND: "$cond" <> "AL" :LAND: "$cond" <> "" :LAND: ((psrtype :AND: &410000) = &10000)
[ "$sabug" <> "unsafe" [ "$sabug" <> "unsafe"
! 0, "mymsr inserting NOP for StrongARM MSR CPSR_c bug" ! 0, "mymsr inserting NOP for StrongARM MSR CPSR_c bug", 1
] ]
NOP NOP
] ]
......
; Copyright 2016 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Machine-independent builds, for 26 bit OS versions
GBLS Machine
Machine SETS "26"
GET Hdr:Machine.Machine
END
...@@ -49,6 +49,7 @@ M_Omega SETL Machine="Omega" ...@@ -49,6 +49,7 @@ M_Omega SETL Machine="Omega"
M_Peregrine SETL Machine="Peregrine" M_Peregrine SETL Machine="Peregrine"
M_STB3 SETL Machine="STB3" M_STB3 SETL Machine="STB3"
M_STB400 SETL Machine="STB400" M_STB400 SETL Machine="STB400"
GBLL M_26
GBLL M_32 GBLL M_32
GBLL M_All GBLL M_All
GBLL M_All32 GBLL M_All32
...@@ -61,6 +62,7 @@ M_STB400 SETL Machine="STB400" ...@@ -61,6 +62,7 @@ M_STB400 SETL Machine="STB400"
GBLL M_IOMD GBLL M_IOMD
GBLL M_STB5 GBLL M_STB5
GBLL M_Tungsten GBLL M_Tungsten
M_26 SETL Machine="26"
M_32 SETL Machine="32" M_32 SETL Machine="32"
M_All SETL Machine="All" M_All SETL Machine="All"
M_All32 SETL Machine="All32" M_All32 SETL Machine="All32"
...@@ -81,7 +83,7 @@ M_Tungsten SETL Machine="Tungsten" ...@@ -81,7 +83,7 @@ M_Tungsten SETL Machine="Tungsten"
; If true, we mustn't rely on MSR, MRS etc, and we should be ; If true, we mustn't rely on MSR, MRS etc, and we should be
; RISC OS 3.1 compatible. ; RISC OS 3.1 compatible.
GBLL No32bitCode GBLL No32bitCode
No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400 No32bitCode SETL M_26 :LOR: M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega :LOR: M_Peregrine :LOR: M_STB3 :LOR: M_STB400
; Are we only supporting 32bit processor modes? ; Are we only supporting 32bit processor modes?
GBLL No26bitCode GBLL No26bitCode
...@@ -100,9 +102,9 @@ NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9 ...@@ -100,9 +102,9 @@ NoUnaligned SETL M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA8 :LOR: M_CortexA9
; Do we need to deal with the StrongARM conditional MSR CPSR_c bug? ; Do we need to deal with the StrongARM conditional MSR CPSR_c bug?
GBLL StrongARM_MSR_bug GBLL StrongARM_MSR_bug
StrongARM_MSR_bug SETL M_All :LOR: M_All32 :LOR: M_IOMD StrongARM_MSR_bug SETL M_26 :LOR: M_All :LOR: M_All32 :LOR: M_IOMD
[ :LNOT: M_All :LAND: :LNOT: M_All32 [ :LNOT: M_All :LAND: :LNOT: M_All32 :LAND: :LNOT: M_26
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Switches that should not be used by machine-independent code ; Switches that should not be used by machine-independent code
......
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