Commit 79a72575 authored by Ben Avison's avatar Ben Avison

Add a definition of the BEN bit in SCTLR (née MMU control register)

Detail:
The memory barriers ISB, DSB & DMB were intially introduced in ARMv6 as CP15
operations, however they were replaced at ARMv7 with dedicated instructions
and the old CP15 encodings deprecated. Since ARMv7VE was introduced, some CPUs
can be configured to make the CP15 encodings undefined instructions. For
unconfigurable CPUs, the CP15 encodings are always enabled, but for others,
we need to set this bit in SCTLR.

Note, this sort of behaviour usually implies ARM intend on removing these
instructions in a future architecture, so we might need to plan for this
eventuality.

Version 2.78. Tagged as 'HdrSrc-2_78'
parent ad292190
/* (2.77)
/* (2.78)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.77
#define Module_MajorVersion_CMHG 2.78
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 30 May 2018
#define Module_Date_CMHG 24 Jun 2019
#define Module_MajorVersion "2.77"
#define Module_Version 277
#define Module_MajorVersion "2.78"
#define Module_Version 278
#define Module_MinorVersion ""
#define Module_Date "30 May 2018"
#define Module_Date "24 Jun 2019"
#define Module_ApplicationDate "30-May-18"
#define Module_ApplicationDate "24-Jun-19"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.77"
#define Module_HelpVersion "2.77 (30 May 2018)"
#define Module_LibraryVersionInfo "2:77"
#define Module_FullVersion "2.78"
#define Module_HelpVersion "2.78 (24 Jun 2019)"
#define Module_LibraryVersionInfo "2:78"
......@@ -80,7 +80,8 @@ MMUC_A * 1 :SHL: 1 ; 567 Alignment fault enable
MMUC_C * 1 :SHL: 2 ; 567 Cache enable (or Data cache enable)
MMUC_W * 1 :SHL: 3 ; 56 Write buffer enable
MMUC_P * 1 :SHL: 4 ; 5 32-bit program space enable
MMUC_D * 1 :SHL: 5 ; 5 32-bit data space enable
MMUC_D * 1 :SHL: 5 ; 5!! 32-bit data space enable
MMUC_BEN * 1 :SHL: 5 ; !!7 CP15 barrier enable (ARMv7MP)
MMUC_L * 1 :SHL: 6 ; 5 Late abort mode enable
MMUC_B * 1 :SHL: 7 ; 56 Big-endian mode enable
MMUC_S * 1 :SHL: 8 ; 5 S-mode enable
......
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