Commit 625c738d authored by Jeffrey Lee's avatar Jeffrey Lee

Update VMSAv6 definitions

Detail:
  hdr/MEMM/VMSAv6 - Remove XScale-specific L1_X, L2_X, L2L_X flags. Add L2_S flag. Add definitions for the cache size ID register fields.
Admin:
  Tested on ARM11, Cortex-A7, -A8, -A9, -A15


Version 2.52. Tagged as 'HdrSrc-2_52'
parent 8934eabd
/* (2.51)
/* (2.52)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.51
#define Module_MajorVersion_CMHG 2.52
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 18 May 2015
#define Module_Date_CMHG 05 Aug 2015
#define Module_MajorVersion "2.51"
#define Module_Version 251
#define Module_MajorVersion "2.52"
#define Module_Version 252
#define Module_MinorVersion ""
#define Module_Date "18 May 2015"
#define Module_Date "05 Aug 2015"
#define Module_ApplicationDate "18-May-15"
#define Module_ApplicationDate "05-Aug-15"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.51"
#define Module_HelpVersion "2.51 (18 May 2015)"
#define Module_LibraryVersionInfo "2:51"
#define Module_FullVersion "2.52"
#define Module_HelpVersion "2.52 (05 Aug 2015)"
#define Module_LibraryVersionInfo "2:52"
......@@ -57,7 +57,6 @@ L1_C * 1 :SHL: 3 ; cacheable
L1_B * 1 :SHL: 2 ; bufferable
L1_nG * 1 :SHL: 17 ; 1=entry associated with ASID, 0=global
L1_XN * 1 :SHL: 4 ; eXecute Never
L1_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (is TEX bit 0)
L2L_TEXShift * 12 ; For large pages
L2_TEXShift * 6 ; For extended small pages
......@@ -65,11 +64,10 @@ L2L_TEX * 2_111 :SHL: 12 ; Type Extension bits (large pages)
L2_TEX * 2_111 :SHL: 6 ; Type Extension bits (tiny and extended pages)
L2_C * 1 :SHL: 3 ; cacheable bit in level 2 entry
L2_B * 1 :SHL: 2 ; bufferable --------""----------
L2_S * 1 :SHL: 10 ; shareable
L2_nG * 1 :SHL: 11 ; 1=entry associated with ASID, 0=global
L2L_XN * 1 :SHL: 15 ; eXecute Never for large pages
L2_XN * 1 ; eXecute Never for extended small pages
L2L_X * 1 :SHL: 12 ; XScale - modifies meaning of C and B bits (large pages) (is TEX bit 0)
L2_X * 1 :SHL: 6 ; XScale - modifies meaning of C and B bits (tiny and extended pages) (is TEX bit 0)
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
......@@ -120,7 +118,24 @@ CR_Domains CN 3 ; read/write
CR_FaultStatus CN 5 ; read
CR_FaultAddress CN 6 ; read
; Cache type register fields
; Cache size ID register fields
CCSIDR_WT_pos * 31
CCSIDR_WT_mask * 1:SHL:CCSIDR_WT_pos
CCSIDR_WB_pos * 30
CCSIDR_WB_mask * 1:SHL:CCSIDR_WB_pos
CCSIDR_RA_pos * 29
CCSIDR_RA_mask * 1:SHL:CCSIDR_RA_pos
CCSIDR_WA_pos * 28
CCSIDR_WA_mask * 1:SHL:CCSIDR_WA_pos
CCSIDR_NumSets_pos * 13
CCSIDR_NumSets_mask * &7FFF:SHL:CCSIDR_NumSets_pos
CCSIDR_Associativity_pos * 3
CCSIDR_Associativity_mask * &3FF:SHL:CCSIDR_Associativity_pos
CCSIDR_LineSize_pos * 0
CCSIDR_LineSize_mask * 7:SHL:CCSIDR_LineSize_pos
; Cache type register fields (ARMv6 register format)
; NOTE - need to be kept in sync with hdr.MEMM.ARM600!
CT_ctype_pos * 25
......
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