Commit 4bc92abd authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL

Add long descriptor page table definitions

Version 2.86. Tagged as 'HdrSrc-2_86'
parent 3103a302
/* (2.85)
/* (2.86)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 2.85
#define Module_MajorVersion_CMHG 2.86
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 09 Nov 2019
#define Module_Date_CMHG 16 Nov 2019
#define Module_MajorVersion "2.85"
#define Module_Version 285
#define Module_MajorVersion "2.86"
#define Module_Version 286
#define Module_MinorVersion ""
#define Module_Date "09 Nov 2019"
#define Module_Date "16 Nov 2019"
#define Module_ApplicationDate "09-Nov-19"
#define Module_ApplicationDate "16-Nov-19"
#define Module_ComponentName "HdrSrc"
#define Module_FullVersion "2.85"
#define Module_HelpVersion "2.85 (09 Nov 2019)"
#define Module_LibraryVersionInfo "2:85"
#define Module_FullVersion "2.86"
#define Module_HelpVersion "2.86 (16 Nov 2019)"
#define Module_LibraryVersionInfo "2:86"
......@@ -20,6 +20,11 @@
; 18-Feb-09 JL Created, using ARM600 as basis.
; ------------------------------------------------
;
; Short descriptor page table format
;
; Access privilege bits
; These comprise the AP and APX bits, which are luckily always in the same location relative to each other
......@@ -76,6 +81,90 @@ L2_nG * 1 :SHL: 11 ; 1=entry associated with ASID, 0=global
L2L_XN * 1 :SHL: 15 ; eXecute Never for large pages
L2_XN * 1 ; eXecute Never for extended small pages
; ------------------------------------------------
;
; Long descriptor page table format
;
; Common definitions for all three translation levels
LL_TypeMask * 4_3 ; Bits 0-1 indicate entry type
LL_Fault * 4_0 ; Translation fault
LL12_Block * 4_1 ; L1/L2 block mapping. Invalid for L3.
LL12_Table * 4_3 ; Pointer to L2 or L3 page table
LL3_Page * 4_3 ; L3 page mapping. Invalid for L1/L2.
LL_LowAttr * &00000FFC ; 10 bits of attributes in low half
LL_LowAttr_Start * 2
LL_LowAttr_Size * 10
LL_HighAttr * &FFF00000 ; 12 bits of attributes in high half
LL_HighAttr_Start * 20
LL_HighAttr_Size * 12
LL_LowAddr * &FFFFF000 ; 20 address bits in low half (PA 12-31)
LL_LowAddr_Start * 12
LL_LowAddr_Size * 20
LL_HighAddr * &000000FF ; 8 address bits in high half (PA 32-39)
LL_HighAddr_Start * 0
LL_HighAddr_Size * 8
; Table attributes
LL_Table_HighAttr_NS_bit * 63-32 ; Entire sub-tree is Non-Secure
LL_Table_HighAttr_APTable1_bit * 62-32 ; Entire sub-tree is read-only
LL_Table_HighAttr_APTable0_bit * 61-32 ; Entire sub-tree is privileged-only
LL_Table_HighAttr_XN_bit * 60-32 ; Entire sub-tree is eXecute Never
LL_Table_HighAttr_PXN_bit * 59-32 ; Entire sub-tree is Privileged XN
LL_Table_HighAttr_NS * 1:SHL:LL_Table_HighAttr_NS_bit
LL_Table_HighAttr_APTable1 * 1:SHL:LL_Table_HighAttr_APTable1_bit
LL_Table_HighAttr_APTable0 * 1:SHL:LL_Table_HighAttr_APTable0_bit
LL_Table_HighAttr_XN * 1:SHL:LL_Table_HighAttr_XN_bit
LL_Table_HighAttr_PXN * 1:SHL:LL_Table_HighAttr_PXN_bit
; Page attributes
LL_Page_HighAttr_SW3_bit * 58-32 ; Four bits reserved for software use
LL_Page_HighAttr_SW2_bit * 57-32
LL_Page_HighAttr_SW1_bit * 56-32
LL_Page_HighAttr_SW0_bit * 55-32
LL_Page_HighAttr_XN_bit * 54-32 ; eXecute Never
LL_Page_HighAttr_PXN_bit * 53-32 ; Privileged eXecute Never
LL_Page_HighAttr_Contig_bit * 52-32 ; Hint that 16 adjacent entries are physically contiguous (c.f. large pages in short-descriptor format)
LL_Page_LowAttr_nG_bit * 11 ; non-Global (1=ASID tagged, 0=global)
LL_Page_LowAttr_AF_bit * 10 ; Access flag
LL_Page_LowAttr_SH1_bit * 9 ; Shareability: 00=non-shareable
LL_Page_LowAttr_SH0_bit * 8 ; 10=outer shareable, 11=inner shareable
LL_Page_LowAttr_AP2_bit * 7 ; Read-only
LL_Page_LowAttr_AP1_bit * 6 ; 1=Unprivileged access, 0=Privileged only
LL_Page_LowAttr_NS_bit * 5 ; Non-Secure
LL_Page_LowAttr_AttrIndx2_bit * 4 ; 1=use MAIR1, 0=use MAIR0
LL_Page_LowAttr_AttrIndx1_bit * 3 ; Bits 0 & 1 give index within MAIR register
LL_Page_LowAttr_AttrIndx0_bit * 2
LL_Page_HighAttr_SW3 * 1:SHL:LL_Page_HighAttr_SW3_bit
LL_Page_HighAttr_SW2 * 1:SHL:LL_Page_HighAttr_SW2_bit
LL_Page_HighAttr_SW1 * 1:SHL:LL_Page_HighAttr_SW1_bit
LL_Page_HighAttr_SW0 * 1:SHL:LL_Page_HighAttr_SW0_bit
LL_Page_HighAttr_XN * 1:SHL:LL_Page_HighAttr_XN_bit
LL_Page_HighAttr_PXN * 1:SHL:LL_Page_HighAttr_PXN_bit
LL_Page_HighAttr_Contig * 1:SHL:LL_Page_HighAttr_Contig_bit
LL_Page_LowAttr_nG * 1:SHL:LL_Page_LowAttr_nG_bit
LL_Page_LowAttr_AF * 1:SHL:LL_Page_LowAttr_AF_bit
LL_Page_LowAttr_SH1 * 1:SHL:LL_Page_LowAttr_SH1_bit
LL_Page_LowAttr_SH0 * 1:SHL:LL_Page_LowAttr_SH0_bit
LL_Page_LowAttr_AP2 * 1:SHL:LL_Page_LowAttr_AP2_bit
LL_Page_LowAttr_AP1 * 1:SHL:LL_Page_LowAttr_AP1_bit
LL_Page_LowAttr_NS * 1:SHL:LL_Page_LowAttr_NS_bit
LL_Page_LowAttr_AttrIndx2 * 1:SHL:LL_Page_LowAttr_AttrIndx2_bit
LL_Page_LowAttr_AttrIndx1 * 1:SHL:LL_Page_LowAttr_AttrIndx1_bit
LL_Page_LowAttr_AttrIndx0 * 1:SHL:LL_Page_LowAttr_AttrIndx0_bit
; ------------------------------------------------
;
; Other definitions
;
; CP15 control register bits
; Retaining MMUC_* naming for compatability with existing code
......
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