Commit 15c9ad3f authored by Steve Revill's avatar Steve Revill

CortexA7 is missing from the HiResTTX switch. This means on Titanium

MODE 7 doesn't really work because the DVI framer chip can't clock
as low as 13.5MHz for 320x200.

Version 2.64. Tagged as 'HdrSrc-2_64'
parent 7d0f8d91
/* (2.63)
/* (2.64)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.63
#define Module_MajorVersion_CMHG 2.64
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 28 May 2016
#define Module_Date_CMHG 05 Jun 2016
#define Module_MajorVersion "2.63"
#define Module_Version 263
#define Module_MajorVersion "2.64"
#define Module_Version 264
#define Module_MinorVersion ""
#define Module_Date "28 May 2016"
#define Module_Date "05 Jun 2016"
#define Module_ApplicationDate "28-May-16"
#define Module_ApplicationDate "05-Jun-16"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.63"
#define Module_HelpVersion "2.63 (28 May 2016)"
#define Module_LibraryVersionInfo "2:63"
#define Module_FullVersion "2.64"
#define Module_HelpVersion "2.64 (05 Jun 2016)"
#define Module_LibraryVersionInfo "2:64"
......@@ -255,7 +255,7 @@ MorrisSupport SETL {TRUE}
; Less blocky teletext font
GBLL HiResTTX
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi
HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten :LOR: M_ARM11ZF :LOR: M_RPi :LOR: M_CortexA7
; Teletext rendered at 8bpp
GBLL TTX256
......
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