1. 23 Mar, 2013 1 commit
    • Ben Avison's avatar
      First of a two-part update of Hdr:CPU.Generic* · 154397df
      Ben Avison authored
      Detail:
        Changes split into two parts to make the diffs readable. In this part:
        * Simplified the inclusion of Hdr:Machine.<Machine> - all current builds
          require a new enough version of objasm that the bug with GET directives
          inside conditionals appears to no longer apply.
        * A number of macros used to have large switches of almost-identical code
          depending upon whether an optional register was defined or not - these
          are now simplified by using a local variable to hold the register.
        * RETURNS is no longer wrapped in :LNOT: No26bitCode, since it could still
          be useful for exception return, non-transient callback handlers etc.
          However, its presence is still a warning sign for non-32-bit-compatible
          code, so it emits a warning unless you add an extra argument to indicate
          that you've vetted that the code is 32-bit safe.
        * Operator precedence bug fixed in SCPSR from Generic32 copied across to
          Generic26 (applies if bits to set/clear were given as expressions).
        * Conflicting set and clear bits in SCPSR now produce an error in both
          Generic26 and Generic32 (previously was only a warning in Generic26).
        * Added the same flag bit check in WritePSRc in Generic26 as already
          existed in Generic32.
        * Some comments reformatted for consistency.
        * Uses of mymrs replaced with MRS, and unconditional or flag-only uses of
          mymsr macro replaced with MSR (other ones remain to deal with the
          StrongARM bug).
        * RETURNVC and RETURNVS no longer accept NV condition code.
        * Removed BKPT macro (now implemented natively in objasm).
      Admin:
        Update originally from Rob Sprowson, bugfixed and split into two parts by me.
      
      Version 2.25. Tagged as 'HdrSrc-2_25'
      154397df
  2. 11 May, 2001 1 commit
    • Ben Avison's avatar
      Some maintenance of Hdr:CPU.GenericXX. · d7d188f6
      Ben Avison authored
      Detail:
        * Added register definitions for the new registers in those wacky new ARM2
          chips, r8_fiq and r9_fiq.
        * Added abort and undefined mode register definitions using the ARM ARM
          standardised suffix of _abt and _und (previously we only had _abort and
          _undef versions).
        * Added some sanity checking of the fields parameter to the RestPSR macro,
          to help warn the unwary of the effect of compiling No32bitCode.
      Admin:
        Changes appear to function as desired. Debug builds of MPEGDriver actually
        require those extra register definitions.
      
      Version 1.23. Tagged as 'HdrSrc-1_23'
      d7d188f6
  3. 16 Nov, 2000 1 commit
  4. 01 Jun, 2000 1 commit
    • Stewart Brodie's avatar
      Added TOGPSRR macro · 4d65da6c
      Stewart Brodie authored
      Detail:
        TOGPSRR does the same as TOGPSR except that the bits to toggle
          are held in a register.
        Hdr:Sprite contains declarations that are mistranslated by Hdr2H 1.1.
          Hdr2H has been updated to handle these declarations and is first
          present in RiscOS/Library 0.45.
      Admin:
        Required by DualSerial 0.24 and later.
        Requires Library 0.45 to export a correct C version of Hdr:Sprite
      
      Version 0.88. Tagged as 'HdrSrc-0_88'
      4d65da6c
  5. 17 May, 2000 2 commits
  6. 15 May, 2000 1 commit
    • Stewart Brodie's avatar
      SavePSR functionality incorporated into some other macros. · 71b4a945
      Stewart Brodie authored
      Detail:
        Improved some of the PSR wiggling macros with an optional extra
          register into which to save the old PSR.  Saves an extra MRS
          instruction in some cases.
        Some macros changed to invoke SavePSR macro instead of having a copy
          of the macro body.
      Admin:
        Required by ScrBlank 2.30.
      
      Version 0.83. Tagged as 'HdrSrc-0_83'
      71b4a945
  7. 04 Apr, 2000 1 commit
  8. 26 Jan, 2000 1 commit
  9. 09 Dec, 1999 1 commit
    • Stewart Brodie's avatar
      26-bit version of WritePSRc macro was missing the third parameter · 09a7194a
      Stewart Brodie authored
      Detail:
        The 32-bit version of WritePSRc takes an optional third parameter
          which is the condition code to embed in the instruction.
          The 26-bit mode version now takes the same parameters, thus
          allowing Sound2 (SoundScheduler) to build.
      Admin:
        Tested in Phoebe and 32 machine builds of Sound2.
        Required by SoundScheduler 1.25 and later (Sound2-1_25)
      
      Version 0.65. Tagged as 'HdrSrc-0_65'
      09a7194a
  10. 26 Nov, 1999 1 commit
    • Stewart Brodie's avatar
      Merge of 32-bit capable macros to trunk. · 559a684e
      Stewart Brodie authored
      Detail:
        The 26-bit and 32-bit capable macros have been added.
        Header files choose which set of macros to use based on <Machine>.
        If you want the new macros, include "Hdr:APCS.<APCS>" in addition
          to the usual inclusions at the top of assembler files.
        Choices are based on the settings of macros No32bitCode and
          No26bitCode.  By default, all existing machines define these
          as {TRUE} and {FALSE} respectively.  This yields the same macros
          as before (tested in Customer F 5 build) and should yield code which
          functions on RISC OS 3.1.  Any other combination of settings is
          untested at this time.
        New assembler code should use the macros FunctionEntry, Return et al
          to ensure that they build correctly.
        New assembler code should be written to not require flag preservation
          across internal function calls and to not assume it on external
          function calls where it is possible to do so.  DO NOT simply replace
          "MOVS pc, lr" with "MOV pc...
      559a684e
  11. 05 Nov, 1996 1 commit