diff --git a/VersionNum b/VersionNum
index d27825097c10d3ccbbebc4afdc4bcb460355d14f..c32e8d795828c6ff93e23068a9fd44e3699d16b1 100644
--- a/VersionNum
+++ b/VersionNum
@@ -1,21 +1,21 @@
-/* (2.79)
+/* (2.80)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  *
  */
-#define Module_MajorVersion_CMHG        2.79
+#define Module_MajorVersion_CMHG        2.80
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                15 Jul 2019
+#define Module_Date_CMHG                19 Aug 2019
 
-#define Module_MajorVersion             "2.79"
-#define Module_Version                  279
+#define Module_MajorVersion             "2.80"
+#define Module_Version                  280
 #define Module_MinorVersion             ""
-#define Module_Date                     "15 Jul 2019"
+#define Module_Date                     "19 Aug 2019"
 
-#define Module_ApplicationDate          "15-Jul-19"
+#define Module_ApplicationDate          "19-Aug-19"
 
 #define Module_ComponentName            "HdrSrc"
 
-#define Module_FullVersion              "2.79"
-#define Module_HelpVersion              "2.79 (15 Jul 2019)"
-#define Module_LibraryVersionInfo       "2:79"
+#define Module_FullVersion              "2.80"
+#define Module_HelpVersion              "2.80 (19 Aug 2019)"
+#define Module_LibraryVersionInfo       "2:80"
diff --git a/hdr/MEMM/ARM600 b/hdr/MEMM/ARM600
index c469094134c5b96829917c710d1c5ecfa8f1ad29..e1558822c710e722959b0cd7e0fdcd50f425e61c 100644
--- a/hdr/MEMM/ARM600
+++ b/hdr/MEMM/ARM600
@@ -44,7 +44,7 @@ L1_DomainShift *   5            ; lowest bit position in L1 entry for domain num
 
 L1_Fault *      4_0             ; translation fault specifier in L1 entry
 L1_Page *       4_1             ; coarse page specifier in L1 entry
-L1_Section *    4_2             ; section specifier in L1 entry
+L1_Section *    4_2             ; section (or supersection) specifier in L1 entry
 L1_Fine *       4_3             ; fine page specifier in L2 entry
 
 L2_Fault *      4_0             ; translation fault specifier in L2 entry
@@ -60,6 +60,13 @@ L1_P    *       1 :SHL: 9       ; page bit in level 1 entry (XScale - ECC enable
 L1_U    *       1 :SHL: 4       ; updateable bit in level 1 entry (ARM6 only, not ARM7+)
 L1_C    *       1 :SHL: 3       ; cacheable  --------""----------
 L1_B    *       1 :SHL: 2       ; bufferable --------""----------
+L1_SS   *       1 :SHL: 18      ; supersection
+L1_SSb36Shift * 5               ; physical address 39:36 in supersections
+L1_SSb36Width * 4
+L1_SSb36Mask *  1:SHL:(L1_SSb36Shift+L1_SSb36Width) - 1:SHL:L1_SSb36Shift
+L1_SSb32Shift * 20              ; physical address 35:32 in supersections
+L1_SSb32Width * 4
+L1_SSb32Mask *  1:SHL:(L1_SSb32Shift+L1_SSb32Width) - 1:SHL:L1_SSb32Shift
 
 L2L_TEXShift *  12
 L2_TEXShift *   6