Commit c8aa9b4a authored by Ben Avison's avatar Ben Avison
Browse files

Added support for machine-neutral builds

Detail:
  For use when building binaries which must run on a wide range of ARM
  architectures - typically used by disc builds rather than rom builds.
  Use Machine=All to target all machines, or Machine=All32 for any
  architecture from v3 (ARM600) upwards.
Admin:
  Tested in a BuildHost build.

Version 1.69. Tagged as 'HdrSrc-1_69'
parent b9489b71
/* (1.68)
/* (1.69)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 1.68
#define Module_MajorVersion_CMHG 1.69
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 17 May 2009
#define Module_Date_CMHG 14 Jun 2009
#define Module_MajorVersion "1.68"
#define Module_Version 168
#define Module_MajorVersion "1.69"
#define Module_Version 169
#define Module_MinorVersion ""
#define Module_Date "17 May 2009"
#define Module_Date "14 Jun 2009"
#define Module_ApplicationDate "17-May-09"
#define Module_ApplicationDate "14-Jun-09"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "1.68"
#define Module_HelpVersion "1.68 (17 May 2009)"
#define Module_LibraryVersionInfo "1:68"
#define Module_FullVersion "1.69"
#define Module_HelpVersion "1.69 (14 Jun 2009)"
#define Module_LibraryVersionInfo "1:69"
......@@ -439,13 +439,13 @@ MchFlgs_CumulativeNOT SETA MchFlgs_CumulativeNOT :OR: :NOT: MchFlgs
[ "$Machine" = "CortexA9" ; Cortex A9
ArchitectureOption v7_VFP3D32H_SIMD
|
[ "$Machine" = "Any" ; if the target code is required to run on
[ "$Machine" = "All" ; if the target code is required to run on
; any RISC OS machine
ArchitectureOption v2
ArchitectureOption v2a_FPA
ArchitectureOption v7_VFP3D32H_SIMD
|
[ "$Machine" = "Any32" ; if the target code is required to run on
[ "$Machine" = "All32" ; if the target code is required to run on
; any 32-bit capable RISC OS machine
ArchitectureOption v3
ArchitectureOption v3_FPA
......
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Machine-indeoendent builds
GBLS Machine
Machine SETS "All"
GET Hdr:Machine.Machine
END
; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Machine-indeoendent builds
GBLS Machine
Machine SETS "All"
GET Hdr:Machine.Machine
END
......@@ -35,6 +35,7 @@ Included_Hdr_Machine_Machine SETL {TRUE}
; Define boolean variables for each machine to avoid possibility of typos in
; strings. NEVER use these outside this header file. Use feature tests
; instead.
GBLL M_All
GBLL M_Falcon
GBLL M_Morris
GBLL M_Omega
......@@ -46,6 +47,7 @@ Included_Hdr_Machine_Machine SETL {TRUE}
GBLL M_Phoebe
GBLL M_Tungsten
GBLL M_32
M_All SETL Machine="All"
M_Falcon SETL Machine="Falcon"
M_Morris SETL Machine="Morris"
M_Omega SETL Machine="Omega"
......@@ -65,6 +67,7 @@ SystemName SETS "NC OS"
SystemName SETS "RISC OS"
]
[ :LNOT: M_All ; these switches should not be used by machine-independent code
; CPU type (processor model, excluding cache and memory management)
GBLS CPU_Type
CPU_Type SETS "ARM600"
......@@ -122,6 +125,7 @@ HiResTTX SETL M_Lazarus :LOR: M_STB400 :LOR: M_STB5 :LOR: M_Tungsten
GBLL TTX256
TTX256 SETL M_Tungsten :LOR: M_STB5
] ; :LNOT: M_All
; Do we support 26-bit only processors? (ARM2, ARM3)
; If true, we mustn't rely on MSR, MRS etc, and we should be
......@@ -133,6 +137,7 @@ No32bitCode SETL M_Morris :LOR: M_Phoebe :LOR: M_Falcon :LOR: M_Omega :LO
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_Tungsten :LOR: M_STB5
[ :LNOT: M_All
; Are we using a HAL?
GBLL HAL
HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5
......@@ -142,12 +147,14 @@ HAL SETL M_32 :LOR: M_Tungsten :LOR: M_STB5
GBLL HAL32
HAL32 SETL HAL :LAND: No26bitCode
HAL26 SETL HAL :LAND: :LNOT: No26bitCode
] ; :LNOT: M_All
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
NoUnaligned SETL {FALSE}
[ :LNOT: M_All
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; System build options added for STB/NCD
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -634,6 +641,7 @@ POSTFlashesFrontPanelLEDs SETL ((IOMD_C_FrontPanelLED <> 0) :LOR: (IOMD
GBLL MACNVRAM2copies
MACNVRAM2copies SETL {FALSE}
] ; :LNOT: M_All
] ; :LNOT: :DEF: Included_Hdr_Machine_Machine
OPT OldOpt
......
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