Commit aa255886 authored by Kevin Bracey's avatar Kevin Bracey
Browse files

Ursula branch merged. Might not work though.

Version 0.29. Tagged as 'HdrSrc-0_29'
parent 430611ee
/* (0.28)
/* (0.29)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 0.28
#define Module_MajorVersion_CMHG 0.29
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 16 Aug 1999
#define Module_Date_CMHG 17 Aug 1999
#define Module_MajorVersion "0.28"
#define Module_Version 28
#define Module_MajorVersion "0.29"
#define Module_Version 29
#define Module_MinorVersion ""
#define Module_Date "16 Aug 1999"
#define Module_Date "17 Aug 1999"
#define Module_FullVersion "0.28"
#define Module_FullVersion "0.29"
......@@ -29,8 +29,21 @@
; 09-Aug-93 SMC Added base addresses for EASI space.
; 19-Oct-93 TMD Added IOMD_ProtectionLinkBit
; 06-May-94 RCM Added extra registers provided by MORRIS
; 13-Jun_94 RCM Added more MORRIS bits
; 13-Jun-94 RCM Added more MORRIS bits
; 22-Nov-94 RCM Added more MORRIS bits
; 08-Mar-95 RCM Added IOMD_VIDMUX
; 08-Mar-95 RCM Added IOMD_SoundsystemLinkBit
; 06-Feb-96 SMC Added Morris IRQC registers
; 15-May-96 BAR Added 'Half' spped clock prescaler variables.
; 17-Jun-96 BAR Added IOMD ID Version numbers.
; 09-Jul-96 BAR Added New constants for ROM speed selection.
; 11-Jul-96 TMD Added ASTCR and new DRAMWID bits
; ---------
; 03-Dec-96 RWB RiscOS merge project - added the following from RiscOS370 tree
; IOMD_ATODICR, IOMD_ATODSR, IOMD_ATODCC, IOMD_ATODCNT1,
; IOMD_ATODCNT2, IOMD_ATODCNT3, IOMD_ATODCNT4, IOMD_VIDINITB,
; IOMD_VIDCR_Dup
; 09-Jun-98 MJS rename as IOMD (was IOMDL), add IOMD2 definitions
[ :LNOT: :DEF: IOMD_Base
......@@ -45,11 +58,19 @@ IOMD_Base SETA &03200000 ; Same address as IOC was
; Offsets within IOMD
IOMD_KBDCR * &008 ; Keyboard control
IOMD_CLINES * &00C ; General purpose IO register with Monitor Id in bit 0
[ MorrisSupport
IOMD_IDLEMODE * &01C
IOMD_STOPMODE * &02C
IOMD_CLKCTL * &03C
]
[ MorrisSupport
IOMD_IRQSTC * &060 ; IRQ C interrupts status
IOMD_IRQRQC * &064 ; IRQ C interrupts request
IOMD_IRQMSKC * &068 ; IRQ C interrupts mask
IOMD_VIDMUX * &06C ; Video LCD and Serial Sound Mux control
IOMD_IRQSTD * &070 ; IRQ D interrupts status
IOMD_IRQRQD * &074 ; IRQ D interrupts request
IOMD_IRQMSKD * &078 ; IRQ D interrupts mask
......@@ -78,8 +99,17 @@ IOMD_ECTCR * &0C8 ; Expansion card timing control
IOMD_DMAEXT * &0CC ; DMA external control
[ MorrisSupport
IOMD_ASTCR * &0CC ; I/O asynchronous timing control - same address as old DMAEXT on IOMD
IOMD_DRAMWID * &0D0 ; DRAM width control
IOMD_SELFREF * &0D4 ; DRAM Self Refresh control
IOMD_ATODICR * &0E0
IOMD_ATODSR * &0E4
IOMD_ATODCC * &0E8
IOMD_ATODCNT1 * &0EC
IOMD_ATODCNT2 * &0F0
IOMD_ATODCNT3 * &0F4
IOMD_ATODCNT4 * &0F8
]
IOMD_IO0CURA * &100 ; I/O DMA 0 CurA
......@@ -132,6 +162,7 @@ IOMD_VIDEND * &1D4 ; End
IOMD_VIDSTART * &1D8 ; Start
IOMD_VIDINIT * &1DC ; Init
IOMD_VIDCR * &1E0 ; Control
IOMD_VIDINITB * &1E8 ; InitB (for dual-scan LCDs)
IOMD_DMASTA * &1F0 ; DMA Interrupt Status
IOMD_DMAREQ * &1F4 ; Request
......@@ -140,9 +171,13 @@ IOMD_DMAMSK * &1F8 ; Mask
[ MorrisSupport
; Bits in CLKCTL (Clock Prescaler Control)
IOMD_CLKCTL_CpuclkNormal * 1 :SHL: 2 ; 0=div2, 1=div1
IOMD_CLKCTL_MemclkNormal * 1 :SHL: 1 ; 0=div2, 1=div1
IOMD_CLKCTL_IOclkNormal * 1 :SHL: 0 ; 0=div2, 1=div1
IOMD_CLKCTL_CpuclkNormal * 1 :SHL: 2 ; 1=div1
IOMD_CLKCTL_MemclkNormal * 1 :SHL: 1 ; 1=div1
IOMD_CLKCTL_IOclkNormal * 1 :SHL: 0 ; 1=div1
IOMD_CLKCTL_CpuclkHalf * 0 :SHL: 2 ; 0=div2
IOMD_CLKCTL_MemclkHalf * 0 :SHL: 1 ; 0=div2
IOMD_CLKCTL_IOclkHalf * 0 :SHL: 0 ; 0=div2
]
; Bits in IOCR (I/O Control Register)
......@@ -186,9 +221,11 @@ IOMD_HardDisc_IRQ_bit * 1 :SHL: 1 ; Hard disc (IDE) IRQ
[ MorrisSupport
; Bits in IRQ register D
IOMD_AtoD_IRQ_bit * 1 :SHL: 2 ; A to D (Joystick) IRQ request
IOMD_Nevent2_bit * 1 :SHL: 4 ;
IOMD_Nevent1_bit * 1 :SHL: 3 ;
IOMD_AtoD_IRQ_bit * 1 :SHL: 2 ; A to D (Joystick) IRQ request
IOMD_MouseTxEmpty_IRQ_bit * 1 :SHL: 1 ; PS2 Mouse port Tx empty IRQ request
IOMD_MouseRxFull_IRQ_bit * 1 :SHL: 0 ; PS2 Mouse port Rx full IRQ request
IOMD_MouseRxFull_IRQ_bit * 1 :SHL: 0 ; PS2 Mouse port Rx full IRQ request
]
; Bits in FIQ register
......@@ -198,17 +235,29 @@ IOMD_ext_FIQ_bit * 1 :SHL: 1 ; Extended FIQ request
; Values to store in ROM control registers (0 and 1)
IOMD_ROMCR_218 * 0 :SHL: 0
IOMD_ROMCR_187 * 1 :SHL: 0
IOMD_ROMCR_156 * 2 :SHL: 0
IOMD_ROMCR_125 * 3 :SHL: 0
IOMD_ROMCR_93 * 4 :SHL: 0
IOMD_ROMCR_62 * 5 :SHL: 0
IOMD_ROMCR_BurstOff * 0 :SHL: 3 ; burst mode off
IOMD_ROMCR_Burst125 * 1 :SHL: 3 ; 125 ns burst
IOMD_ROMCR_Burst93 * 2 :SHL: 3 ; 93.75 ns burst
IOMD_ROMCR_Burst62 * 3 :SHL: 3 ; 62.5 ns burst
IOMD_ROMCR_NSTicks_7 * 0 :SHL: 0
IOMD_ROMCR_NSTicks_6 * 1 :SHL: 0
IOMD_ROMCR_NSTicks_5 * 2 :SHL: 0
IOMD_ROMCR_NSTicks_4 * 3 :SHL: 0
IOMD_ROMCR_NSTicks_3 * 4 :SHL: 0
IOMD_ROMCR_NSTicks_2 * 5 :SHL: 0
IOMD_ROMCR_218 * IOMD_ROMCR_NSTicks_7
IOMD_ROMCR_187 * IOMD_ROMCR_NSTicks_6
IOMD_ROMCR_156 * IOMD_ROMCR_NSTicks_5
IOMD_ROMCR_125 * IOMD_ROMCR_NSTicks_4
IOMD_ROMCR_93 * IOMD_ROMCR_NSTicks_3
IOMD_ROMCR_62 * IOMD_ROMCR_NSTicks_2
IOMD_ROMCR_BTicks_0 * 0 :SHL: 3
IOMD_ROMCR_BTicks_4 * 1 :SHL: 3
IOMD_ROMCR_BTicks_3 * 2 :SHL: 3
IOMD_ROMCR_BTicks_2 * 3 :SHL: 3
IOMD_ROMCR_BurstOff * IOMD_ROMCR_BTicks_0 ; burst mode off
IOMD_ROMCR_Burst125 * IOMD_ROMCR_BTicks_4 ; 125 ns burst
IOMD_ROMCR_Burst93 * IOMD_ROMCR_BTicks_3 ; 93.75 ns burst
IOMD_ROMCR_Burst62 * IOMD_ROMCR_BTicks_2 ; 62.5 ns burst
[ MorrisSupport
IOMD_ROMCR_HalfSpeed * 0 :SHL: 5
......@@ -232,6 +281,25 @@ IOMD_VREFCR_REF_128 * 8 :SHL: 0 ; 128
[ MorrisSupport
IOMD_DRAMWID_DRAM_32bit * 0 :SHL: 0 ; 32bit
IOMD_DRAMWID_DRAM_16bit * 1 :SHL: 0 ; 16bit
; The following bits are new to ARM7500FE
; Note that the ARM7500FE data sheet now refers to this register as DRAMCR
; but that name clashes with the earlier DRAMCR on IOMD
IOMD_DRAMWID_EDO_Enable * 1 :SHL: 4 ; enable use of EDO DRAM
IOMD_DRAMWID_RASCAS_2 * 0 :SHL: 5 ; 2 memory clock cycles from falling nRAS
; to falling nCAS
IOMD_DRAMWID_RASCAS_3 * 1 :SHL: 5 ; 3 memory clock cycles from falling nRAS
; to falling nCAS
IOMD_DRAMWID_RASPre_3 * 0 :SHL: 6 ; 3 memory clock cycles guaranteed RAS precharge
IOMD_DRAMWID_RASPre_4 * 1 :SHL: 6 ; 4 memory clock cycles guaranteed RAS precharge
; Values to put in ASTCR
IOMD_ASTCR_Minimal * 0 :SHL: 7 ; minimal delay to I/O cycles
IOMD_ASTCR_WaitStates * 1 :SHL: 7 ; add wait states to cope with fast MEMCLK
]
; Bits in IOTCR
......@@ -284,12 +352,19 @@ IOMD_DMA_SD1 * 1 :SHL: 5
IOMD_VIDCR_DRAMMode * 1 :SHL: 6 ; set for DRAM, clear for VRAM
IOMD_VIDCR_Enable * 1 :SHL: 5
IOMD_VIDCR_Dup * 1 :SHL: 7
; Bits in DRAMCR
IOMD_DRAMCR_DRAM_Large * 4_00 ; 1M, 4M, 16M DRAM
IOMD_DRAMCR_DRAM_Small * 4_01 ; 256K DRAM
[ MorrisSupport
IOMD_Original * &D4E7
IOMD_7500 * &5B98
IOMD_7500FE * &AA7C
]
; Registers not strictly in IOMD, but in IOMD-based systems
IOMD_MonitorType * &03310000
......@@ -309,6 +384,45 @@ IOMD_EASI_Base5 * &0D000000
IOMD_EASI_Base6 * &0E000000
IOMD_EASI_Base7 * &0F000000
; *************
; *** IOMD2 ***
; *************
;Chip ID in registers &94,&98 (low,high)
;
IOMD_IOMD2 * &D5E8
;IOMD2 specific registers
;
IOMD2_IOCR * &000 ;I/O control (synonym for IOC IOCControl)
IOMD2_PRECHG * &0D0 ;SDRAM precharge trigger
IOMD2_SDTMG * &0D4 ;SDRAM timing control
IOMD2_SDMODE * &0D8 ;SDRAM mode
IOMD2_VRAMTMG * &0E0 ;VRAM timing
IOMD2_SCDIV * &0E4 ;SC clock divider
IOMD2_SDRAMCR * &0EC ;SDRAM mapping
IOMD2_BMPRTY * &0F4 ;bus master priority
IOMD2_BMSPD * &0F8 ;bus master speed
IOMD2_PROCID * &0FC ;processor id
IOMD2_DMASTA * &1F0 ;DMA interrupt status (32 bit)
IOMD2_DMAREQ * &1F4 ;DMA interrupt request (32 bit)
IOMD2_DMAENBL * &1F8 ;DMA interrupt enable (32 bit)
IOMD2_VIDMRD * &300 ;VRAM read access flag
IOMD2_VFLGLO * &304 ;VRAM flag low address
IOMD2_VFLGHI * &308 ;VRAM flag high address
IOMD2_INTSTA * &310 ;interrupt status (32 bit)
IOMD2_INTREQ * &314 ;interrupt request (32 bit)
IOMD2_INTENBL * &318 ;interrupt enable (32 bit)
IOMD2_INTLVL * &31C ;interrupt level modes
]
END
; Copyright 1997 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
SUBT Definition of machines that can run RISC OS Ursula
GBLS Machine
Machine SETS "Phoebe"
GET Hdr:Machine.Machine
END
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