Skip to content

GitLab

HdrSrc
HdrSrc
Commit 7a505e55 authored by Ben Avison's avatar Ben Avison
Browse files
Options

Bugfix to macros in Hdr:CPU.Generic32 

Detail:
  A number of these macros, when build targeting all CPUs (e.g. in disc builds)
  only worked correctly if a register was specified to leave the original
  PSR state in.
Admin:
  Untested, but no risk to ROM builds.

Version 2.28. Tagged as 'HdrSrc-2_28'
parent d8b7c3f3
Hide whitespace changes
Inline Side-by-side
Showing with 35 additions and 50 deletions
VersionNum
View file @ 7a505e55
/* (2.27)
/* (2.28)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.27
#define Module_MajorVersion_CMHG 2.28
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 06 Apr 2013
#define Module_Date_CMHG 29 Apr 2013
#define Module_MajorVersion "2.27"
#define Module_Version 227
#define Module_MajorVersion "2.28"
#define Module_Version 228
#define Module_MinorVersion ""
#define Module_Date "06 Apr 2013"
#define Module_Date "29 Apr 2013"
#define Module_ApplicationDate "06-Apr-13"
#define Module_ApplicationDate "29-Apr-13"
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.27"
#define Module_HelpVersion "2.27 (06 Apr 2013)"
#define Module_LibraryVersionInfo "2:27"
#define Module_FullVersion "2.28"
#define Module_HelpVersion "2.28 (29 Apr 2013)"
#define Module_LibraryVersionInfo "2:28"
hdr/CPU/Generic32
View file @ 7a505e55
......@@ -153,15 +153,12 @@ $label
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
BIC $regtmp, $regtmp, #$bits
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
BIC $regtmp, $srcreg, #$bits
TEQP $regtmp, #0
B %FT02
01
......@@ -390,18 +387,15 @@ $label
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
[ (($set) :OR: ($clr)) = ARM_CC_Mask
TEQ$cond.P pc, #$set ; All change, so skip the clear operation
|
ORR$cond $regtmp, $regtmp, #($set) :OR: ($clr)
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
]
B %FT02
......@@ -557,15 +551,12 @@ $label
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
ORR $regtmp, $regtmp, #$bits
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
ORR $regtmp, $srcreg, #$bits
TEQP $regtmp, #0
B %FT02
01
......@@ -631,15 +622,12 @@ $label
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
TEQP $regtmp, #$bits
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
TEQP $srcreg, #$bits
B %FT02
01
EOR $regtmp, $srcreg, #CPU32_bits
......@@ -677,15 +665,12 @@ $label
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MOV $srcreg, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
TEQP $regtog, $regtmp
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z if ARMv3 or later
BNE %FT01
TEQP $regtog, $srcreg
B %FT02
01
EOR $regtmp, $srcreg, $regtog
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment