Commit 726bd695 authored by Ben Avison's avatar Ben Avison

Second of a two-part update of HdrSrc.

Detail:
  Hdr:System:
  * Hdr:CPU.Arch added to the list of header files included here. This is
    because it's now needed by Hdr:CPU.Generic*.
  Hdr:CPU.Generic*:
  * Reintroduced ARMv2 compatibility to many macros. Should allow a new
    universal boot sequence to be constructed.
  * SCPSR in Generic26 optimised in cases where no PSR bits are preserved.
  * RemovePSRFromReg optimised for 32bit-only builds - becomes a no-op.
  Hdr:Machine.Machine:
  * Reordering of braces so that symbol "HAL" doesn't have to be defined -
    useful for disc builds, which target both HAL and non-HAL machines, so
    the symbol is undefined.
  * Added some comments and an assert about No26bitCode and No32bitCode.
Admin:
  Update originally from Rob Sprowson, bugfixes and additions and split into
  two parts by me.

Version 2.26. Tagged as 'HdrSrc-2_26'
parent 154397df
/* (2.25)
/* (2.26)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 2.25
#define Module_MajorVersion_CMHG 2.26
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 23 Mar 2013
#define Module_MajorVersion "2.25"
#define Module_Version 225
#define Module_MajorVersion "2.26"
#define Module_Version 226
#define Module_MinorVersion ""
#define Module_Date "23 Mar 2013"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "HdrSrc"
#define Module_ComponentPath "castle/RiscOS/Sources/Programmer/HdrSrc"
#define Module_FullVersion "2.25"
#define Module_HelpVersion "2.25 (23 Mar 2013)"
#define Module_LibraryVersionInfo "2:25"
#define Module_FullVersion "2.26"
#define Module_HelpVersion "2.26 (23 Mar 2013)"
#define Module_LibraryVersionInfo "2:26"
......@@ -351,9 +351,17 @@ srcreg SETS "$oldpsr"
[ (($set) :AND: ($clr)) <> 0
! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
]
$label MOV$cond $srcreg, pc
$label
[ (($set) :OR: ($clr)) = ARM_CC_Mask
[ "$oldpsr" <> ""
MOV$cond $oldpsr, pc
]
TEQ$cond.P pc, #$set ; All change, so skip the clear operation
|
MOV$cond $srcreg, pc
ORR$cond $regtmp, $srcreg, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
]
MEND
; **********************************************
......@@ -473,12 +481,21 @@ dst SETS "$pcr"
[ No32bitCode
BIC $dst, $pcr, #ARM_CC_Mask ; 32-bit OK: inside No32bitCode macro
|
[ No26bitCode
[ $dst <> $pcr
MOV $dst, $pcr
]
|
[ NoARMv3
MOV $tmp, #0
]
MRS $tmp, CPSR
MVN $tmp, $tmp, LSR #4 ; bit 0 set in *26, clear in *32
MOV $tmp, $tmp, LSL #31 ; shift to top bit
MOV $tmp, $tmp, ASR #7 ; duplicate to top 8 bits
BIC $dst, $pcr, $tmp, ROR #30 ; remove PSR bits if in 26-bit mode
]
]
MEND
......
......@@ -118,7 +118,19 @@ $psr32 SETA (($psr) :AND: :NOT: (I_bit:OR:F_bit)) :OR: ((($psr) :AND: (I_bit
; ************************************************
MACRO
$label CLC $cond
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
CMN pc, #0 ; CLC in 26 bit modes
MSR CPSR_f, #0 ; ARMv3+ does CLC, NOP on ARMv2
01
|
$label MSR$cond CPSR_f, #0
]
MEND
; ***********************************************
......@@ -134,6 +146,35 @@ srcreg SETS "$regtmp"
srcreg SETS "$oldpsr"
]
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
BIC $regtmp, $regtmp, #$bits
TEQP $regtmp, #0
B %FT02
01
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
BIC $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
BIC $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
BIC $regtmp, $srcreg, #CPU32_bits
]
somemsr AL, CPSR, $regtmp, CPU32_bits
02
|
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
......@@ -143,6 +184,7 @@ $label MRS$cond $srcreg, CPSR
BIC$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
]
MEND
; **************************************************
......@@ -150,7 +192,19 @@ $label MRS$cond $srcreg, CPSR
; **************************************************
MACRO
$label CLRV $cond
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
CMP pc, #0 ; CLRV in 26 bit modes
MSR CPSR_f, #C_bit ; ARMv3+ does CLRV, NOP on ARMv2
01
|
$label MSR$cond CPSR_f, #C_bit
]
MEND
; **********************************************************************************
......@@ -167,6 +221,16 @@ usereg SETS "R14"
usereg SETS "$register"
]
$label
[ NoARMv3
TEQ pc, pc ; Can only PHPSEI in non user mode
BEQ %FT01
MOV $usereg, #I_bit
TST $usereg, PC ; is I_bit set ?
TEQEQP $usereg, PC ; no, then set it (and $register = I_bit)
MOVNE $usereg, #0 ; yes, then leave alone (and $register = 0)
B %FT02
01
]
[ "$regtmp" = "" :LOR: StrongARM_MSR_bug
MRS $usereg, CPSR
TST $usereg, #I32_bit ; is I32_bit set?
......@@ -179,6 +243,7 @@ $label
ORREQ $regtmp, $usereg, #I32_bit ; no, then set it
mymsr EQ, CPSR_c, $regtmp ; $register contains original PSR
]
02
MEND
; **************************************************************************
......@@ -193,7 +258,14 @@ usereg SETS "R14"
|
usereg SETS "$register"
]
[ NoARMv3
$label TEQ pc, pc ; Can only PLP in non user mode
mymsr EQ, CPSR_c, $usereg, , safe ; Is a NOP pre ARMv3
TEQNEP $usereg, PC
NOP
|
$label MSR CPSR_c, $usereg
]
MEND
; ******************
......@@ -202,6 +274,20 @@ $label MSR CPSR_c, $usereg
MACRO
$label RETURNVC $cond
$label
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
TEQ r0, r0 ; Incase in user mode
TEQ pc, pc
BICNES pc, lr, #V_bit
MSR CPSR_f, #0
MOV pc, lr
01
|
[ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
......@@ -226,6 +312,7 @@ $label
MOV pc, lr
01
]
]
MEND
; ******************
......@@ -234,6 +321,20 @@ $label
MACRO
$label RETURNVS $cond
$label
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
TEQ r0, r0 ; Incase in user mode
TEQ pc, pc
ORRNES pc, lr, #V_bit
MSR CPSR_f, #V_bit
MOV pc, lr
01
|
[ "$cond" = "NV"
! 1, "Deprecated use of NV condition code in RETURNVC"
]
......@@ -262,6 +363,7 @@ $label
MOV pc, lr
01
]
]
MEND
; ****************************************************
......@@ -281,6 +383,52 @@ srcreg SETS "$oldpsr"
[ (($set) :AND: ($clr)) <> 0
! 1, "Attempt to simultaneously set and clear a bit in SCPSR"
]
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
[ (($set) :OR: ($clr)) = ARM_CC_Mask
TEQ$cond.P pc, #$set ; All change, so skip the clear operation
|
ORR$cond $regtmp, $regtmp, #($set) :OR: ($clr)
TEQ$cond.P $regtmp, #$clr
]
B %FT02
01
[ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000
ORR$cond $regtmp, $regtmp, #CPU32_set :AND: &0FFFFFFF
srcreg SETS "$regtmp"
|
[ CPU32_set <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set
srcreg SETS "$regtmp"
]
]
[ (CPU32_clr :AND: &F0000000) <> 0 :LAND: (CPU32_clr :AND: &F0) <> 0
BIC$cond $regtmp, $srcreg, #CPU32_clr :AND: &F0000000
BIC$cond $regtmp, $regtmp, #CPU32_clr :AND: &0FFFFFFF
srcreg SETS "$regtmp"
|
[ CPU32_clr <> 0
BIC$cond $regtmp, $srcreg, #CPU32_clr
srcreg SETS "$regtmp"
]
]
somemsr $cond, CPSR, $srcreg, CPU32_set:OR:CPU32_clr, unsafe
02
|
$label MRS$cond $srcreg, CPSR
[ (CPU32_set :AND: &F0000000) <> 0 :LAND: (CPU32_set :AND: &F0) <> 0
ORR$cond $regtmp, $srcreg, #CPU32_set :AND: &F0000000
......@@ -303,6 +451,7 @@ srcreg SETS "$regtmp"
]
]
somemsr $cond, CPSR,$srcreg, CPU32_set:OR:CPU32_clr, unsafe
]
MEND
; ****************************************************
......@@ -311,7 +460,12 @@ srcreg SETS "$regtmp"
; ****************************************************
MACRO
$label SavePSR $reg, $cond
[ NoARMv3
$label MOV$cond $reg, pc ; Benign on ARMv3+
MRS$cond $reg, CPSR ; NOP prior to ARMv3
|
$label MRS$cond $reg, CPSR
]
MEND
; ****************************************************
......@@ -338,7 +492,29 @@ field SETS "f"
field SETS "$fields"
]
]
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
; The save sequences for CLRPSR, SCPSR, SETPSR, TOGPSR, TOGPSRR
; and WritePSRc are arranged such that the saved value prefers the one from MRS.
; 26 bit mode pre ARMv3 => saved value is the pc
; 26 bit mode ARMv3/ARMv4 => saved value is from the CPSR
; 32 bit mode => saved value is from the CPSR
; So we want to know if MSR/MRS is supported rather than if running in 32 bit mode
TEQ r0, r0 ; Set Z
MSR CPSR_f, #0 ; Clear Z (if MSR supported)
BNE %FT01
TEQP pc, $reg ; Let the following MSR be the NOP
01
MSR CPSR_cf, $reg
02
|
$label mymsr $cond, CPSR_$field, $reg, , unsafe
]
MEND
; **********************************************
......@@ -346,7 +522,19 @@ $label mymsr $cond, CPSR_$field, $reg, , unsafe
; **********************************************
MACRO
$label SEC $cond
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
CMP pc, #0 ; SEC in 26 bit modes
MSR CPSR_f, #C_bit ; ARMv3+ does SEC, NOP on ARMv2
01
|
$label MSR$cond CPSR_f, #C_bit
]
MEND
; ************************************************
......@@ -362,6 +550,35 @@ srcreg SETS "$regtmp"
srcreg SETS "$oldpsr"
]
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
ORR $regtmp, $regtmp, #$bits
TEQP $regtmp, #0
B %FT02
01
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
ORR $regtmp, $srcreg, #CPU32_bits :AND: &F0000000
ORR $regtmp, $regtmp, #CPU32_bits :AND: &0FFFFFFF
|
ORR $regtmp, $srcreg, #CPU32_bits
]
somemsr AL, CPSR, $regtmp, CPU32_bits
02
|
$label MRS$cond $srcreg, CPSR
[ (CPU32_bits :AND: &F0000000) <> 0 :LAND: (CPU32_bits :AND: &F0) <> 0
; Can't be expressed as a single ARM immediate constant
......@@ -371,6 +588,7 @@ $label MRS$cond $srcreg, CPSR
ORR$cond $regtmp, $srcreg, #CPU32_bits
]
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
]
MEND
; **************************************************
......@@ -378,7 +596,19 @@ $label MRS$cond $srcreg, CPSR
; **************************************************
MACRO
$label SETV $cond
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT01 ; Go round when $cond-itional
]
CMP pc, #&80000000 ; SETV in 26 bit modes
MSR CPSR_f, #N_bit+V_bit ; ARMv3+ does SETV, NOP on ARMv2
01
|
$label MSR$cond CPSR_f, #N_bit+V_bit
]
MEND
; *********************************************************
......@@ -394,9 +624,32 @@ srcreg SETS "$regtmp"
srcreg SETS "$oldpsr"
]
CPU32_bits PSRto32 $bits ; Map to 32 bit PSR
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
TEQP $regtmp, #$bits
B %FT02
01
EOR $regtmp, $srcreg, #CPU32_bits
somemsr AL, CPSR, $regtmp, CPU32_bits
02
|
$label MRS$cond $srcreg, CPSR
EOR$cond $regtmp, $srcreg, #CPU32_bits
somemsr $cond, CPSR, $regtmp, CPU32_bits, unsafe
]
MEND
; ************************************************
......@@ -417,9 +670,32 @@ srcreg SETS "$regtmp"
|
srcreg SETS "$oldpsr"
]
[ NoARMv3
$label
[ "$cond"<>"" :LAND: "$cond"<>"AL"
LCLS rcc
rcc SETS :REVERSE_CC:"$cond"
B$rcc %FT02 ; Go round when $cond-itional
]
MOV $srcreg, #T32_bit ; Invalid CPSR setting detects if MRS is a NOP
MOV $regtmp, pc ; Snapshot 26-bit PSR
MRS $srcreg, CPSR ; Snapshot 32-bit PSR, or NOP pre ARMv3
TEQ $srcreg, #T32_bit
BNE %FT01 ; Branch because Z flag might be in $bits
[ "$oldpsr" <> ""
MOV $srcreg, $regtmp
]
TEQP $regtog, $regtmp
B %FT02
01
EOR $regtmp, $srcreg, $regtog
MSR CPSR_$field, $regtmp
02
|
$label MRS$cond $srcreg, CPSR
EOR$cond $regtmp, $srcreg, $regtog
mymsr $cond, CPSR_$field, $regtmp, , unsafe
]
MEND
; *************************************************
......
......@@ -80,6 +80,12 @@ No32bitCode SETL M_Archimedes :LOR: M_Morris :LOR: M_Falcon :LOR: M_Omega
GBLL No26bitCode
No26bitCode SETL M_32 :LOR: M_Lazarus :LOR: M_IOMD :LOR: M_Tungsten :LOR: M_STB5 :LOR: M_ARM11ZF :LOR: M_CortexA8 :LOR: M_CortexA9
; If this makes your head hurt, the other way of looking at it is
; 26/32 neutral => No32bitCode FALSE No26bitCode FALSE
; 32 only => No32bitCode FALSE No26bitCode TRUE
; 26 only => No32bitCode TRUE No26bitCode FALSE
ASSERT :LNOT: (No26bitCode :LAND: No32bitCode)
; Override optimisation settings to avoid using unaligned LDR(H)/STR(H) on ARMv6+
; This switch should only be enabled for debugging purposes
GBLL NoUnaligned
......@@ -89,7 +95,7 @@ NoUnaligned SETL M_CortexA8 :LOR: M_ARM11ZF :LOR: M_CortexA9
GBLL StrongARM_MSR_bug
StrongARM_MSR_bug SETL M_All :LOR: M_All32 :LOR: M_IOMD
[ :LNOT: M_All :LAND: :LNOT: M_All32
[ :LNOT: M_All :LAND: :LNOT: M_All32
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Switches that should not be used by machine-independent code
......@@ -287,9 +293,8 @@ PAL_Columns SETA 720
PAL_Columns SETA 768
]
]
] ; :LNOT: M_All :LAND: :LNOT: M_All32
[ :LNOT: HAL
[ :LNOT: HAL
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Switches that are pre-HAL & due for retirement
......@@ -318,9 +323,9 @@ FECPUSpeedNormal SETL M_STB3 :LOR: M_STB400 :LOR: M_Lazarus
GBLL FEIOSpeedHalf
FEIOSpeedHalf SETL M_Lazarus
] ; :LNOT: HAL
] ; :LNOT: HAL
[ STB :LAND: :LNOT: HAL
[ STB :LAND: :LNOT: HAL
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Switches that are pre-HAL set top box & due for retirement
......@@ -615,7 +620,8 @@ POSTFlashesFrontPanelLEDs SETL ((IOMD_C_FrontPanelLED <> 0) :LOR: (IOMD
GBLL MACNVRAM2copies
MACNVRAM2copies SETL {FALSE}
] ; STB :LAND: :LNOT: HAL
] ; STB :LAND: :LNOT: HAL
] ; :LNOT: M_All :LAND: :LNOT: M_All32
] ; :LNOT: :DEF: Included_Hdr_Machine_Machine
OPT OldOpt
......
......@@ -15,6 +15,7 @@
TTL Fake Hdr:System
GET Hdr:SWIs
GET Hdr:CPU.Arch
GET Hdr:CPU.Generic26
GET Hdr:CPU.Generic32
GET Hdr:IO.GenericIO
......
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